Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 Analog Block Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IHRCEN : IHRC enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable IHRC
1 : Enable
Enable IHRC
End of enumeration elements list.
ELSEN : ELS XTAL enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable ELS Xtal
1 : Enable
Enable ELS Xtal
End of enumeration elements list.
EHSEN : EHS XTAL enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Disable EHS Xtal
1 : Enable
Enable EHS Xtal
End of enumeration elements list.
EHSFREQ : EHS XTAL frequency range
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Low
Less equal than 12MHz
1 : High
Greater than 12MHz
End of enumeration elements list.
AUEHSEN : Audio external high-speed clock enable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Disable AUEHS X'TAL
1 : Enable
Enable AUEHS X'TAL
End of enumeration elements list.
AUEHSFREQ : AUEHS X'TAL Frequency range
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : AUEHS X'TAL less equal than 12MHz
None
1 : AUEHS X'TAL more than 12MHz
None
0 : AUEHS X'TAL less equal than 12MHz
1 : AUEHS X'TAL more than 12MHz
End of enumeration elements list.
Offset:0x10 AHB Clock Prescale Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHBPRE : AHB clock source prescaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : 0000b
FAHB=FSYSCLK/1
1 : 0001b
FAHB=FSYSCLK/2
2 : 0010b
FAHB=FSYSCLK/4
3 : 0011b
FAHB=FSYSCLK/8
4 : 0100b
FAHB=FSYSCLK/16
5 : 0101b
FAHB=FSYSCLK/32
6 : 0110b
FAHB=FSYSCLK/64
7 : 0111b
FAHB=FSYSCLK/128
8 : 1000b
FAHB=FSYSCLK/256
9 : 1001b
FAHB=FSYSCLK/512
End of enumeration elements list.
Offset:0x14 System Reset Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRSTF : Software reset flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
No SW reset occurred
1 : 1
SW reset occurred
End of enumeration elements list.
WDTRSTF : WDT reset flag
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
No WDT reset occurred
1 : 1
WDT reset occurred
End of enumeration elements list.
LVDRSTF : LVD reset flag
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
No LVD reset occurred
1 : 1
LVD reset occurred
End of enumeration elements list.
EXTRSTF : External reset flag
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
No Extenral reset occurred
1 : 1
External reset occurred
End of enumeration elements list.
PORRSTF : POR reset flag
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : 0
No POR occurred
1 : 1
POR occurred
End of enumeration elements list.
Offset:0x18 LVD Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDRSTLVL : LVD reset level
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 2.00V
LVD reset threshold is 2.00V
1 : 2.40V
LVD reset threshold is 2.40V
2 : 2.70V
LVD reset threshold is 2.70V
End of enumeration elements list.
LVDINTLVL : LVD interrupt level
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : 2.00V
LVD interrupt threshold is 2.00V
1 : 2.40V
LVD interrupt threshold is 2.40V
2 : 2.70V
LVD interrupt threshold is 2.70V
3 : 3.00V
LVD interrupt threshold is 3.00V
End of enumeration elements list.
LVDRSTEN : LVD Reset enable
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : Diable
Disable LVD reset
1 : Enable
Enable LVD reset
End of enumeration elements list.
LVDEN : LVD enable
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : Diable
Disable LVD
1 : Enable
Enable LVD
End of enumeration elements list.
Offset:0x1C External Reset Pin Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESETDIS : External reset pin disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Enable
P0.15 acts as External Reset pin
1 : Disable
P0.15 acts as GPIO pin
End of enumeration elements list.
Offset:0x20 SWD Pin Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWDDIS : SWD pin disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Enable
Enable SWD pins
1 : Disable
Disable SWD pins
End of enumeration elements list.
Offset:0x04 PLL Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSEL : M: 3~31
bits : 0 - 4 (5 bit)
access : read-write
PSEL : P=PSEL*2
bits : 5 - 12 (8 bit)
access : read-write
Enumeration:
3 : 011b
P=6
4 : 100b
P=8
5 : 101b
P=10
6 : 110b
P=12
7 : 111b
P=14
End of enumeration elements list.
FSEL : F=POWER(2, FSEL)
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : F=1
F=1
1 : F=2
F=2
End of enumeration elements list.
PLLCLKSEL : PLL clock source
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : IHRC
12MHz
1 : EHS XTAL
10MHz~25MHz
End of enumeration elements list.
PLLEN : PLL enable
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : Disable
Disable PLL
1 : Enable
Enable PLL
End of enumeration elements list.
Offset:0x08 Clock Source Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IHRCRDY : IHRC ready flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : 0
IHRC is Not Ready
1 : 1
IHRC is Ready
End of enumeration elements list.
ELSRDY : ELS XTAL ready flag
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : 0
ELS Xtal is Not Ready
1 : 1
ELS Xtal is Ready
End of enumeration elements list.
EHSRDY : EHS XTAL ready flag
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : 0
EHS Xtal is Not Ready
1 : 1
EHS Xtal is Ready
End of enumeration elements list.
PLLRDY : PLL ready flag
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : 0
PLL is Not locked
1 : 1
PLL is locked
End of enumeration elements list.
AUEHSRDY : Audio external high-speed clock ready flag
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
0 : AUEHS not ready
None
1 : AUEHS ready
None
End of enumeration elements list.
Offset:0x0C System Clock Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLKSEL : System clock source selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IHRC
IHRC is system clock
1 : ILRC
ILRC is system clock
2 : EHS XTAL
EHS Xtal is system clock
3 : ELS XTAL
ELS Xtal is system clock
4 : PLL Output
PLL is system clock
End of enumeration elements list.
SYSCLKST : System clock switch status
bits : 4 - 10 (7 bit)
access : read-only
Enumeration:
0 : IHRC
IHRC is used as system clock
1 : ILRC
ILRC is used as system clock
2 : EHS XTAL
EHS XTAL is used as system clock
3 : ELS XTAL
ELS XTAL is used as system clock
4 : PLL
PLL output is used as system clock
End of enumeration elements list.
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