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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SET1

SET2

SET3

SET4

SET5

SET6

SET7

SET8

SET9

SET10

SET11

SET12

SET13

SET14

SET15

SET16

SET18

SET19

SET20

SET21

SET22

SET23

SET24


SET1

Offset:0x540 ADC Setting 1 Register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET1 SET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LB_H

LB_H : AGC Control Low bound setting : High byte
bits : 0 - 7 (8 bit)
access : read-write


SET2

Offset:0x550 ADC Setting 2 Register
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET2 SET2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LB_L

LB_L : AGC Control Low bound setting : Low byte
bits : 0 - 7 (8 bit)
access : read-write


SET3

Offset:0x560 ADC Setting 3 Register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET3 SET3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB_H

HB_H : AGC Control High bound setting : High byte
bits : 0 - 7 (8 bit)
access : read-write


SET4

Offset:0x570 ADC Setting 4 Register
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET4 SET4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HB_L

HB_L : AGC Control High bound setting : Low byte
bits : 0 - 7 (8 bit)
access : read-write


SET5

Offset:0x580 ADC Setting 5 Register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET5 SET5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOR_POD

NOR_POD : AGC Control Gain update period at normal mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 1/Fs x 2^0

None

1 : 1/Fs x 2^1

None

2 : 1/Fs x 2^2

None

3 : 1/Fs x 2^3

None

4 : 1/Fs x 2^4

None

5 : 1/Fs x 2^5

None

6 : 1/Fs x 2^6

None

7 : 1/Fs x 2^7

None

8 : 1/Fs x 2^8

None

9 : 1/Fs x 2^9

None

10 : 1/Fs x 2^10

None

11 : 1/Fs x 2^11

None

12 : 1/Fs x 2^12

None

13 : 1/Fs x 2^13

None

14 : 1/Fs x 2^14

None

15 : 1/Fs x 2^15

None

End of enumeration elements list.


SET6

Offset:0x590 ADC Setting 6 Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET6 SET6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUTE_POD

MUTE_POD : AGC Control Gain update period at mute mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 1/Fs x 2^0

None

1 : 1/Fs x 2^1

None

2 : 1/Fs x 2^2

None

3 : 1/Fs x 2^3

None

4 : 1/Fs x 2^4

None

5 : 1/Fs x 2^5

None

6 : 1/Fs x 2^6

None

7 : 1/Fs x 2^7

None

8 : 1/Fs x 2^8

None

9 : 1/Fs x 2^9

None

10 : 1/Fs x 2^10

None

11 : 1/Fs x 2^11

None

12 : 1/Fs x 2^12

None

13 : 1/Fs x 2^13

None

14 : 1/Fs x 2^14

None

15 : 1/Fs x 2^15

None

End of enumeration elements list.


SET7

Offset:0x5A0 ADC Setting 7 Register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET7 SET7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEARCH_TH_H

SEARCH_TH_H : AGC Control Threshold for activating : High byte
bits : 0 - 7 (8 bit)
access : read-write


SET8

Offset:0x5B0 ADC Setting 8 Register
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET8 SET8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEARCH_TH_L

SEARCH_TH_L : AGC Control Threshold for activating : Low byte
bits : 0 - 7 (8 bit)
access : read-write


SET9

Offset:0x5C0 ADC Setting 9 Register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET9 SET9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUTE_TH_H

MUTE_TH_H : AGC Control Threshold for inactivating : High byte
bits : 0 - 7 (8 bit)
access : read-write


SET10

Offset:0x5D0 ADC Setting 10 Register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET10 SET10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUTE_TH_L

MUTE_TH_L : AGC Control Threshold for inactivating : Low byte
bits : 0 - 7 (8 bit)
access : read-write


SET11

Offset:0x5E0 ADC Setting 11 Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET11 SET11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUTE_CAL_POD

MUTE_CAL_POD : AGC Control Period for inactivating
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 256/Fs x 2^0

None

1 : 256/Fs x 2^1

None

2 : 256/Fs x 2^2

None

3 : 256/Fs x 2^3

None

4 : 256/Fs x 2^4

None

5 : 256/Fs x 2^5

None

6 : 256/Fs x 2^6

None

7 : 256/Fs x 2^7

None

8 : 256/Fs x 2^8

None

9 : 256/Fs x 2^9

None

10 : 256/Fs x 2^10

None

11 : 256/Fs x 2^11

None

12 : 256/Fs x 2^12

None

13 : 256/Fs x 2^13

None

14 : 256/Fs x 2^14

None

15 : 256/Fs x 2^15

None

End of enumeration elements list.


SET12

Offset:0x5F0 ADC Setting 12 Register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET12 SET12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAT_TH

SAT_TH : AGC Control Threshold for ADC saturation
bits : 0 - 3 (4 bit)
access : read-write


SET13

Offset:0x600 ADC Setting 13 Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET13 SET13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAT_POD

SAT_POD : AGC Control Period for ADC saturation
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 1/Fs x 2^0

None

1 : 1/Fs x 2^1

None

2 : 1/Fs x 2^2

None

3 : 1/Fs x 2^3

None

4 : 1/Fs x 2^4

None

5 : 1/Fs x 2^5

None

6 : 1/Fs x 2^6

None

7 : 1/Fs x 2^7

None

8 : 1/Fs x 2^8

None

9 : 1/Fs x 2^9

None

10 : 1/Fs x 2^10

None

11 : 1/Fs x 2^11

None

12 : 1/Fs x 2^12

None

13 : 1/Fs x 2^13

None

14 : 1/Fs x 2^14

None

15 : 1/Fs x 2^15

None

End of enumeration elements list.


SET14

Offset:0x610 ADC Setting 14 Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET14 SET14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA_SET_VAL BOOST_SET_VAL AGC_OFF

PGA_SET_VAL : AGC Control PGA setting value at normal mode(1.5dB/step)
bits : 0 - 4 (5 bit)
access : read-write

BOOST_SET_VAL : AGC Control Boost setting value at normal mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : +0dB

None

1 : +12dB

None

2 : +20dB

None

3 : +30dB

None

End of enumeration elements list.

AGC_OFF : AGC Control function
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Enable

None

1 : Disable

None

End of enumeration elements list.


SET15

Offset:0x620 ADC Setting 15 Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET15 SET15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWL ACTIVE

IWL : World length of DAI
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 16-bits

None

1 : 18-bits

None

2 : 20-bits

None

3 : 24-bits

None

End of enumeration elements list.

ACTIVE : Digital Audio Interface Control
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.


SET16

Offset:0x630 ADC Setting 16 Register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET16 SET16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA BOOST

PGA : PGA setting value(1.5dB/step)
bits : 0 - 4 (5 bit)
access : read-write

BOOST : Boost setting value
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : +0dB

None

1 : +12dB

None

2 : +20dB

None

3 : +30dB

None

End of enumeration elements list.


SET18

Offset:0x650 ADC Setting 18 Register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET18 SET18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUTE_CTRL VOL_CTRL

MUTE_CTRL : Digital volume attenuation control at mute mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0dB

None

1 : -3dB

None

2 : -6dB

None

3 : -9dB

None

4 : -12dB

None

5 : -15dB

None

6 : -18dB

None

7 : -21dB

None

8 : -24dB

None

9 : -27dB

None

10 : -30dB

None

11 : -36dB

None

12 : -42dB

None

13 : -48dB

None

14 : -54dB

None

15 : -78dB

None

End of enumeration elements list.

VOL_CTRL : Digital volume attenuation control at normal mode
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

0 : 0dB

None

1 : -3dB

None

2 : -6dB

None

3 : -9dB

None

4 : -12dB

None

5 : -15dB

None

6 : -18dB

None

7 : -21dB

None

8 : -24dB

None

9 : -27dB

None

10 : -30dB

None

11 : -36dB

None

12 : -42dB

None

13 : -48dB

None

14 : -54dB

None

15 : -78dB

None

End of enumeration elements list.


SET19

Offset:0x660 ADC Setting 19 Register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET19 SET19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA_MUTE_VAL BOOST_MUTE_VAL

PGA_MUTE_VAL : PGA setting value at mute mode(1.5dB/step)
bits : 0 - 4 (5 bit)
access : read-write

BOOST_MUTE_VAL : Boost setting value at mute mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : +0dB

None

1 : +12dB

None

2 : +20dB

None

3 : +30dB

None

End of enumeration elements list.


SET20

Offset:0x670 ADC Setting 20 Register
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET20 SET20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOL_MUTE_POD_L VOL_MUTE_POD_H

VOL_MUTE_POD_L : Period for Digital volume attenuation at mute mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 1/Fs x 2^0

None

1 : 1/Fs x 2^1

None

2 : 1/Fs x 2^2

None

3 : 1/Fs x 2^3

None

4 : 1/Fs x 2^4

None

5 : 1/Fs x 2^5

None

6 : 1/Fs x 2^6

None

7 : 1/Fs x 2^7

None

8 : 1/Fs x 2^8

None

9 : 1/Fs x 2^9

None

10 : 1/Fs x 2^10

None

11 : 1/Fs x 2^11

None

12 : 1/Fs x 2^12

None

13 : 1/Fs x 2^13

None

14 : 1/Fs x 2^14

None

15 : 1/Fs x 2^15

None

End of enumeration elements list.

VOL_MUTE_POD_H : Period for Digital volume attenuation at normal mode
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

0 : 1/Fs x 2^0

None

1 : 1/Fs x 2^1

None

2 : 1/Fs x 2^2

None

3 : 1/Fs x 2^3

None

4 : 1/Fs x 2^4

None

5 : 1/Fs x 2^5

None

6 : 1/Fs x 2^6

None

7 : 1/Fs x 2^7

None

8 : 1/Fs x 2^8

None

9 : 1/Fs x 2^9

None

10 : 1/Fs x 2^10

None

11 : 1/Fs x 2^11

None

12 : 1/Fs x 2^12

None

13 : 1/Fs x 2^13

None

14 : 1/Fs x 2^14

None

15 : 1/Fs x 2^15

None

End of enumeration elements list.


SET21

Offset:0x6B0 ADC Setting 21 Register
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET21 SET21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA_EN MICBT_EN ADC_EN

PGA_EN : PGA power-on enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.

MICBT_EN : MICBOOST power-on enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.

ADC_EN : ADC power-on enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.


SET22

Offset:0x6C0 ADC Setting 22 Register
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET22 SET22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CK_EN MICB_EN VREF_EN IREF_EN

CK_EN : CKGEN enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.

MICB_EN : Microphone bias enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.

VREF_EN : VREF circuit enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.

IREF_EN : IREF circuit enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.


SET23

Offset:0x6D0 ADC Setting 23 Register
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET23 SET23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL_MIX_MIC SEL_MIC SEL_MICB

SEL_MIX_MIC : Microphone input path to mixer enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.

SEL_MIC : P1.7/MIC_P and P1.8/MIC_N function selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : General purpose IO

None

1 : Microphone Differential input

None

End of enumeration elements list.

SEL_MICB : Microphone Bias Output select
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : 0.8*VA

None

1 : 0.9*VA

None

End of enumeration elements list.


SET24

Offset:0x6E0 ADC Setting 24 Register
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SET24 SET24 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA_AGC BOOST_AGC

PGA_AGC : PGA setting value when AGC is on
bits : 0 - 4 (5 bit)
access : read-only

BOOST_AGC : Boost setting value when AGC is on
bits : 5 - 11 (7 bit)
access : read-only



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