\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x000 DAC Setting 1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VMIDSEL : Normal mode/Fast Start-up select
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Normal mode
None
1 : Fast Start-up mode
None
End of enumeration elements list.
PD_VREF : VREF Circuit Power-down enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
PD_IREF : IREF Circuit Power-down enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
PD_CLK : CKGEN Power-down enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
PD_DAC : DAC Power-down enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
Offset:0x010 DAC Setting 2 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFT_RSTN : Software reset digital circuit(one MCLK pulse trigger)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Reset
None
1 : Not Reset
None
End of enumeration elements list.
DAC_EN_IN : DAC Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
MUTX : Mute ON/OFF
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Mute off
None
1 : Mute on
None
End of enumeration elements list.
RMP : Attenuation ramp rate
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : 1*LRCK
None
1 : 2*LRCK
None
2 : 4*LRCK
None
3 : 8*LRCK
None
End of enumeration elements list.
Offset:0x020 DAC Setting 3 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VOL : DAC VOL setting
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x030 DAC Setting 4 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INI_RAM_EN : Initialize RAM enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
DEMS : Select the DAC de-emphasis response curve
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
1 : De-emphasis for 48KHz
None
2 : De-emphasis for 44.1KHz
None
3 : De-emphasis for 32KHz
None
End of enumeration elements list.
PD_DRV : Driver Power-down enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
None
1 : Enable
None
End of enumeration elements list.
Offset:0x040 DAC Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Ini_RAM_Ready : Initialize RAM ready
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Not ready
None
1 : Ready
None
End of enumeration elements list.
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