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CMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CMPM

CMP_IE

CMP_RIS

CMP_IC


CMPM

Offset:0x00 Comparator Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM CMPM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMCH CMPS CMPG CMPOEN CMDB CMPOUT CMPEN

CMCH : Comparator negative input pin control bit (CMPEN must be 1 )
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : CM0

Comparator negative input pin is P2.0

1 : CM1

Comparator negative input pin is P2.1

2 : CM2

Comparator negative input pin is P2.2

3 : CM3

Comparator negative input pin is P2.3

4 : CM4

Comparator negative input pin is P2.4

5 : CM5

Comparator negative input pin is P2.5

6 : CM6

Comparator negative input pin is P2.6

7 : CM7

Comparator negative input pin is P2.7

8 : CM8

Comparator negative input pin is P2.8

9 : CM9

Comparator negative input pin is P2.9

10 : CM10

Comparator negative input pin is P2.10

11 : CM11

Comparator negative input pin is P2.11

12 : CM12

Comparator negative input pin is P2.12

13 : CM13

Comparator negative input pin is P2.13

14 : CM14

Comparator negative input pin is P2.14

15 : CM15

Comparator negative input pin is P2.15

16 : CM16

Comparator negative input pin is P3.0

17 : CM17

Comparator negative input pin is P3.1

18 : CM18

Comparator negative input pin is P3.2

19 : CM19

Comparator negative input pin is P3.3

20 : CM20

Comparator negative input pin is P3.4

21 : CM21

Comparator negative input pin is P3.5

22 : CM22

Comparator negative input pin is P3.6

23 : CM23

Comparator negative input pin is P3.7

End of enumeration elements list.

CMPS : Comparator positive input voltage control bit
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : 1/4*Vdd

Internal 1/4*Vdd and enable internal reference voltage generato

1 : 1/2*Vdd

Internal 1/2*Vdd and enable internal reference voltage generator

3 : 3/4*Vdd

Internal 3/4*Vdd and enable internal reference voltage generator

3 : 3/4*Vdd

Internal 3/4*Vdd and enable internal reference voltage generator

End of enumeration elements list.

CMPG : Comparator interrupt trigger direction control bit
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : Rising edge

Rising edge trigger (CMPP larger than CMPN or comparator internal reference voltage)

1 : Falling edge

Falling edge trigger (CMPP less than CMPN or comparator internal reference voltage)

End of enumeration elements list.

CMPOEN : Comparator output pin control bit
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : Disable

CMO pin is GPIO mode

1 : Enable

Enable comparator output pin (P3.8 pin exchanges to comparator output pin and GPIO function is isolated)

End of enumeration elements list.

CMDB : Comparator output debounce time select bit(TCHEN=1 is HCLK, TCHEN=0 is CMP_PCLK)
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : 1*CMP_PCLK

Comparator output debounce time = 1*CMP_PCLK

01 : 2*CMP_PCLK

Comparator output debounce time = 2*CMP_PCLK

2 : 3*CMP_PCLK

Comparator output debounce time = 3*CMP_PCLK

3 : No-debounce

Comparator output debounce time = 0

End of enumeration elements list.

CMPOUT : Comparator output flag bit (The comparator output status is 1 as comparator disable)
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

0 : Comparator internal reference voltage is less than CMPN voltage

None

1 : Comparator internal reference voltage is larger than CMPN voltage

None

End of enumeration elements list.

CMPEN : Comparator control bit
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : Disable

P2[15:0], P3[7:0] are GPIO mode

1 : Enable

Comparator negative input pins are controlled by CMCH[4:0] bits

End of enumeration elements list.


CMP_IE

Offset:0x10 Comparator Interrupt Enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP_IE CMP_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPGIE

CMPGIE : Comparator edge trigger interrupt enable (Comparator interrupt trigger direction refer to CMPG)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

None

1 : Enable

None

End of enumeration elements list.


CMP_RIS

Offset:0x14 Comparator Interrupt Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CMP_RIS CMP_RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPGIF

CMPGIF : Comparator edge trigger interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No interrupt

Comparator edge trigger doesn't occur

1 : Met interrupt requirements

Comparator edge trigger occurs

End of enumeration elements list.


CMP_IC

Offset:0x18 Comparator Interrupt Clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMP_IC CMP_IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPGIC

CMPGIC : Comparator CMPGIF interrupt flag clear
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

None

1 : Clear

Clear CMPGIF bit

End of enumeration elements list.



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