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CMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

RIS

IC

VIREF

OS

IE


CTRL

Offset:0x00 CMP Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0EN CM0PREF CM0RS CM0OEN CM0G CM1EN CM1PREF CM1RS CM1OEN CM1G

CM0EN : CMP0 Enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP0

1 : Enable

Enable CMP0

End of enumeration elements list.

CM0PREF : CMP0 Positive reference voltage (VPREF0) source
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : VIREF0

VPREF0=VIREF0

1 : CM0P

CM0P is VPREF0 input pin.

End of enumeration elements list.

CM0RS : CMP0 internal reference voltage (VIREF0) selection bits
bits : 2 - 7 (6 bit)
access : read-write

Enumeration:

0 : 0000b

VIREF0=VIREF

1 : 0001b

VIREF0=VIREF*1/16

2 : 0010b

VIREF0=VIREF*2/16

3 : 0011b

VIREF0=VIREF*3/16

4 : 0100b

VIREF0=VIREF*4/16

5 : 0101b

VIREF0=VIREF*5/16

6 : 0110b

VIREF0=VIREF*6/16

7 : 0111b

VIREF0=VIREF*7/16

8 : 1000b

VIREF0=VIREF*8/16

9 : 1001b

VIREF0=VIREF*9/16

10 : 1010b

VIREF0=VIREF*10/16

11 : 1011b

VIREF0=VIREF*11/16

12 : 1100b

VIREF0=VIREF*12/16

13 : 1101b

VIREF0=VIREF*13/16

14 : 1110b

VIREF0=VIREF*14/16

15 : 1111b

VIREF0=VIREF*15/16

End of enumeration elements list.

CM0OEN : CMP0 Output pin control bit
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Disable CM0O

1 : Enable

Enable CM0O

End of enumeration elements list.

CM0G : CMP0 interrupt trigger direction control bit
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Falling range trigger

CMP0 output status is from high to low as VPREF0 less than CM0N

1 : Rising edge trigger

CMP0 output status is from low to high as VPREF0 more than CM0N

End of enumeration elements list.

CM1EN : CMP1 Enable bit
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP1

1 : Enable

Enable CMP1

End of enumeration elements list.

CM1PREF : CMP1 Positive reference voltage (VPREF1) source
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : VIREF1

VPREF1=VIREF1

1 : CM1P

CM1P is VPREF1 input pin.

End of enumeration elements list.

CM1RS : CMP1 internal reference voltage (VIREF1) selection bits
bits : 10 - 23 (14 bit)
access : read-write

Enumeration:

0 : 0000b

VIREF1=VIREF

1 : 0001b

VIREF1=VIREF*1/16

2 : 0010b

VIREF1=VIREF*2/16

3 : 0011b

VIREF1=VIREF*3/16

4 : 0100b

VIREF1=VIREF*4/16

5 : 0101b

VIREF1=VIREF*5/16

6 : 0110b

VIREF1=VIREF*6/16

7 : 0111b

VIREF1=VIREF*7/16

8 : 1000b

VIREF1=VIREF*8/16

9 : 1001b

VIREF1=VIREF*9/16

10 : 1010b

VIREF1=VIREF*10/16

11 : 1011b

VIREF1=VIREF*11/16

12 : 1100b

VIREF1=VIREF*12/16

13 : 1101b

VIREF1=VIREF*13/16

14 : 1110b

VIREF1=VIREF*14/16

15 : 1111b

VIREF1=VIREF*15/16

End of enumeration elements list.

CM1OEN : CMP1 Output pin control bit
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

0 : Disable

Disable CM1O

1 : Enable

Enable CM1O

End of enumeration elements list.

CM1G : CMP1 interrupt trigger direction control bit
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Falling range trigger

CMP1 output status is from high to low as VPREF1 less than CM1N

1 : Rising edge trigger

CMP1 output status is from low to high as VPREF1 more than CM1N

End of enumeration elements list.


RIS

Offset:0x10 CMP n Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IF CM1IF

CM0IF : CMP0 raw interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on CMP0

1 : Met interrupt requirements

Interrupt requirements met on CMP0

End of enumeration elements list.

CM1IF : CMP1 raw interrupt flag
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on CMP1

1 : Met interrupt requirements

Interrupt requirements met on CMP1

End of enumeration elements list.


IC

Offset:0x14 CMP Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IC IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IC CM1IC

CM0IC : CMP0 interrupt flag clear bit
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CMP0 interrupt flag

End of enumeration elements list.

CM1IC : CMP1 interrupt flag clear bit
bits : 1 - 2 (2 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CMP1 interrupt flag

End of enumeration elements list.


VIREF

Offset:0x04 CMP Internal Reference Voltage register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VIREF VIREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPIREFEN CMPIREF

CMPIREFEN : CMP internal reference voltage (VIREF) enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP internal reference voltage

1 : Enable

Enable CMP internal reference voltage

End of enumeration elements list.

CMPIREF : CMP internal reference voltage (VIREF) source
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : VDD

VIREF=VDD

1 : Internal 3V

VIREF=Internal 3V

End of enumeration elements list.


OS

Offset:0x08 CMP Output Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OS OS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0OUT CM1OUT

CM0OUT : CMP0 Output flag bit
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : CMP0 positive voltage is less than CM0N voltage

VPREF0 is less than CM0N voltage

1 : CMP0 positive voltage is more than CM0N voltage

VPREF0 is more than CM0N voltage

End of enumeration elements list.

CM1OUT : CMP1 Output flag bit
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : CMP1 positive voltage is less than CM1N voltage

VPREF1 is less than CM1N voltage

1 : CMP1 positive voltage is more than CM1N voltage

VPREF1 is more than CM1N voltage

End of enumeration elements list.


IE

Offset:0x0C CMP Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IE CM1IE

CM0IE : CMP0 interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP0 interrupt

1 : Enable

Enable CMP0 interrupt

End of enumeration elements list.

CM1IE : CMP1 interrupt enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP1 interrupt

1 : Enable

Enable CMP1 interrupt

End of enumeration elements list.



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