\n
address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 WDT Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTEN : WDT enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable WDT
1 : Enable
Enable WDT
End of enumeration elements list.
WDTIE : WDT interrupt enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
WDT reset when WDT time-out
1 : Enable
Enable WDT interrupt
End of enumeration elements list.
WDTINT : WDT interrupt flag
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : No
No WDT time-out
1 : WDT time-out
WDT interrupt is triggered if WDTIE=1
End of enumeration elements list.
Offset:0x04 WDT Clock Source Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : WDT clock source
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : IHRC
WDT clock source=IHRC
1 : HCLK
WDT clock source=HCLK
2 : ILRC
WDT clock source=ILRC
3 : ELS XTAL
WDT clock source=ELS XTAL
End of enumeration elements list.
Offset:0x08 WDT Timer Constant Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Watchdog timer constant reload value
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x0C WDT Feed Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FV : Watchdog feed value
bits : 0 - 15 (16 bit)
access : write-only
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