\n
address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 CT32Bn Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Enable Timer Counter and Prescale Counter for counting
End of enumeration elements list.
CRST : Counter Reset
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. This is cleared by HW when the counter reset operation finishes.
End of enumeration elements list.
Offset:0x10 CT32Bn Counter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTM : Counter/Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : Timer Mode
Every rising PCLK edge
2 : Counter Mode
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2 : Counter Mode
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2 : Counter Mode
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
End of enumeration elements list.
CIS : Counter Input Select
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : CT32Bn_CAP0
Counter input from CT32Bn_CAP0
End of enumeration elements list.
Offset:0x14 CT32Bn Match Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0IE : Enable generating an interrupt when MR0 matches TC
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Generating an interrupt when MR0 matches TC
End of enumeration elements list.
MR0RST : Enable reset TC when MR0 matches TC
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Reset TC when MR0 matches TC
End of enumeration elements list.
MR0STOP : Stop TC and PC and clear CEN bit when MR0 matches TC
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
End of enumeration elements list.
MR1IE : Enable generating an interrupt when MR1 matches TC
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Generating an interrupt when MR1 matches TC
End of enumeration elements list.
MR1RST : Enable reset TC when MR1 matches TC
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Reset TC when MR1 matches TC
End of enumeration elements list.
MR1STOP : Stop TC and PC and clear CEN bit when MR1 matches TC
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
End of enumeration elements list.
MR2IE : Enable generating an interrupt when MR2 matches TC
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Generating an interrupt when MR2 matches TC
End of enumeration elements list.
MR2RST : Enable reset TC when MR2 matches TC
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Reset TC when MR2 matches TC
End of enumeration elements list.
MR2STOP : Stop TC and PC and clear CEN bit when MR2 matches TC
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
End of enumeration elements list.
MR3IE : Enable generating an interrupt when MR3 matches TC
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Generating an interrupt when MR3 matches TC
End of enumeration elements list.
MR3RST : Enable reset TC when MR3 matches TC
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Reset TC when MR3 matches TC
End of enumeration elements list.
MR3STOP : Stop TC and PC and clear CEN bit when MR3 matches TC
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
End of enumeration elements list.
Offset:0x18 CT32Bn MR0 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Offset:0x1C CT32Bn MR1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Offset:0x20 CT32Bn MR2 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Offset:0x24 CT32Bn MR3 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Offset:0x28 CT32Bn Capture Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAP0RE : Capture on CT32Bn_CAP0 rising edge
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
A sequence of 0 then 1 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
End of enumeration elements list.
CAP0FE : Capture on CT32Bn_CAP0 falling edge
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
A sequence of 1 then 0 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
End of enumeration elements list.
CAP0IE : Interrupt on CT32Bn_CAP0 event
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
A CAP0 load due to a CT32Bn_CAP0 event will generate an interrupt.
End of enumeration elements list.
CAP0EN : CAP0 function enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Enable CAP0 function
End of enumeration elements list.
Offset:0x2C CT32Bn CAP0 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Offset:0x30 CT32Bn External Match Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT32Bn_PWM0 output.
bits : 0 - 0 (1 bit)
access : read-write
EM1 : When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT32Bn_PWM1 output.
bits : 1 - 2 (2 bit)
access : read-write
EM2 : When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT32Bn_PWM2 output.
bits : 2 - 4 (3 bit)
access : read-write
EM3 : When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT32Bn_PWM3 output.
bits : 3 - 6 (4 bit)
access : read-write
EMC0 : CT32Bn_PWM0 functionality
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : Do Nothing
Do Nothing
1 : Low
CT32Bn_PWM0 pin is LOW
2 : High
CT32Bn_PWM0 pin is HIGH
3 : Toggle
Toggle CT32Bn_PWM0 pin
End of enumeration elements list.
EMC1 : CT32Bn_PWM1 functionality
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : Do Nothing
Do Nothing
1 : Low
CT32Bn_PWM1 pin is LOW
2 : High
CT32Bn_PWM1 pin is HIGH
3 : Toggle
Toggle CT32Bn_PWM1 pin
End of enumeration elements list.
EMC2 : CT32Bn_PWM2 functionality
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : Do Nothing
Do Nothing
1 : Low
CT32Bn_PWM2 pin is LOW
2 : High
CT32Bn_PWM2 pin is HIGH
3 : Toggle
Toggle CT32Bn_PWM2 pin
End of enumeration elements list.
EMC3 : CT32Bn_PWM3 functionality
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : Do Nothing
Do Nothing
1 : Low
CT32Bn_PWM3 pin is LOW
2 : High
CT32Bn_PWM3 pin is HIGH
3 : Toggle
Toggle CT32Bn_PWM3 pin
End of enumeration elements list.
Offset:0x34 CT32Bn PWM Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0EN : PWM0 enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM0 is controlled by EM0
1 : Enable
Enable PWM mode for CT32Bn_PWM0
End of enumeration elements list.
PWM1EN : PWM1 enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM1 is controlled by EM1
1 : Enable
Enable PWM mode for CT32Bn_PWM1
End of enumeration elements list.
PWM2EN : PWM2 enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM2 is controlled by EM2
1 : Enable
Enable PWM mode for CT32Bn_PWM2
End of enumeration elements list.
PWM3EN : PWM3 enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM3 is controlled by EM3
1 : Enable
Enable PWM mode for CT32Bn_PWM3
End of enumeration elements list.
PWM0IOEN : CT32Bn_PWM0/GPIO selection
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM0 pin is act as GPIO
1 : Enable
CT32Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
End of enumeration elements list.
PWM1IOEN : CT16Bn_PWM1/GPIO selection
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM1 pin is act as GPIO
1 : Enable
CT32Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
End of enumeration elements list.
PWM2IOEN : CT32Bn_PWM2/GPIO selection
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM2 pin is act as GPIO
1 : Enable
CT32Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
End of enumeration elements list.
PWM3IOEN : CT32Bn_PWM3/GPIO selection
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : Disable
CT32Bn_PWM3 pin is act as GPIO
1 : Enable
CT32Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
End of enumeration elements list.
Offset:0x38 CT32Bn Raw Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MR0IF : Match channel 0 interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : No
No interrupt on match channel 0
1 : Met interrupt requirements
Interrupt requirements met on match channel 0
End of enumeration elements list.
MR1IF : Match channel 1 interrupt flag
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : No
No interrupt on match channel 1
1 : Met interrupt requirements
Interrupt requirements met on match channel 1
End of enumeration elements list.
MR2IF : Match channel 2 interrupt flag
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : No
No interrupt on match channel 2
1 : Met interrupt requirements
Interrupt requirements met on match channel 2
End of enumeration elements list.
MR3IF : Match channel 3 interrupt flag
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : No
No interrupt on match channel 3
1 : Met interrupt requirements
Interrupt requirements met on match channel 3
End of enumeration elements list.
CAP0IF : Capture channel 0 interrupt flag
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : No
No interrupt on CAP0
1 : Met interrupt requirements
Interrupt requirements met on CAP0
End of enumeration elements list.
Offset:0x3C CT32Bn Interrupt Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MR0IC : MR0IF clear bit
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear MR0IF
End of enumeration elements list.
MR1IC : MR1IF clear bit
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear MR1IF
End of enumeration elements list.
MR2IC : MR2IF clear bit
bits : 2 - 4 (3 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear MR2IF
End of enumeration elements list.
MR3IC : MR3IF clear bit
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear MR3IF
End of enumeration elements list.
CAP0IC : CAP0IF clear bit
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear CAP0IF
End of enumeration elements list.
Offset:0x04 CT32Bn Timer Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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