Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 SSPn Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSPEN : SSP enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable SSP
1 : Enable
Enable SSP
End of enumeration elements list.
LOOPBACK : Loopback mode enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable loopback mode
1 : Enable
Enable loopback mode
End of enumeration elements list.
SDODIS : Slave data out disable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Enable
Enable slave data out
1 : Disble
Diable slave data out (MISO=0)
End of enumeration elements list.
MS : Master/Slave selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Master
Act as Master
1 : Slave
Act as Slave
End of enumeration elements list.
FORMAT : Interface format
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : SPI
SPI
1 : SSI
SSI
End of enumeration elements list.
FRESET : SSP FSM and FIFO Reset
bits : 6 - 13 (8 bit)
access : write-only
Enumeration:
0 : 00b
No effect
3 : 11b
Reset FSM and FIFO
End of enumeration elements list.
DL : Data length = DL[3:0]+1
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
2 : 0010b
Data length=3
3 : 0011b
Data length=4
4 : 0100b
Data length=5
5 : 0101b
Data length=6
6 : 0110b
Data length=7
7 : 0111b
Data length=8
8 : 1000b
Data length=9
9 : 1001b
Data length=10
10 : 1010b
Data length=11
11 : 1011b
Data length=12
12 : 1100b
Data length=13
13 : 1101b
Data length=14
14 : 1110b
Data length=15
15 : 1111b
Data length=16
End of enumeration elements list.
Offset:0x10 SSPn Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOVFIE : RX FIFO overflow interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable RX FIFO overflow interrupt
1 : Enable
Enable RX FIFO overflow interrupt
End of enumeration elements list.
RXTOIE : RX time-out interrupt enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable RX time-out interrupt
1 : Enable
Enable RX time-out interrupt
End of enumeration elements list.
RXHFIE : RX half-full interrupt enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable RX half-full interrupt
1 : Enable
Enable RX half-full interrupt
End of enumeration elements list.
TXHEIE : TX half-empty interrupt enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable TX half-empty interrupt
1 : Enable
Enable TX half-empty interrupt
End of enumeration elements list.
Offset:0x14 SSPn Raw Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXOVFIF : RX FIFO overflow interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : No RXOVF interrupt
No RXOVF interrupt
1 : Met RXOVF interrupt requirements
RXOVF interrupt is triggered when RXOVFIE=1
End of enumeration elements list.
RXTOIF : RX time-out interrupt flag
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : No RXTO interrupt
No RXTO interrupt
1 : Met RXTO interrupt requirements
RXTO interrupt is triggered when RXTOIE=1
End of enumeration elements list.
RXHFIF : RX half-full interrupt flag
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : No
No RXHF interrupt
1 : Met RXHF interrupt requirements
RXHF interrupt is triggered when RXHFIE=1
End of enumeration elements list.
TXHEIF : TX half-empty interrupt flag
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : No
No TXHE interrupt
1 : Met TXHE interrupt requirements
TXHE interrupt is triggered when TXHFIE=1
End of enumeration elements list.
Offset:0x18 SSPn Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXOVFIC : RX FIFO overflow flag clear
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear RXOVF flag
End of enumeration elements list.
RXTOIC : RX time-out interrupt flag clear
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear RXTO flag
End of enumeration elements list.
RXHFIC : RX FIFO half-full interrupt flag clear
bits : 2 - 4 (3 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear RXHF interrupt flag
End of enumeration elements list.
TXHEIC : TX FIFO half-empty interrupt flag clear
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear TXHE interrupt flag
End of enumeration elements list.
Offset:0x1C SSPn Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data : Data
bits : 0 - 15 (16 bit)
access : read-write
Offset:0x20 SPIn Data Fetch Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DF : SPI data fetch control bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Enable when SCKn frequency is higher than 6MHz
End of enumeration elements list.
Offset:0x04 SSPn Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MLSB : MSB/LSB seletion
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MSB
MSB transmit first
1 : LSB
LSB transmit first
End of enumeration elements list.
CPOL : Clock priority selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Low
SCK idles at low level
1 : High
SCK idles at high level
End of enumeration elements list.
CPHA : Clock phase of edge sampling
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CPHA0
The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data
1 : CPHA1
SCK 1st edge is for data transition, and receive/transmit data at 2nd edge
End of enumeration elements list.
Offset:0x08 SSPn Clock Divider Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : SSPn SCK=SSPn_PCLK/(2*DIV+2)
bits : 0 - 7 (8 bit)
access : read-write
Offset:0x0C SSPn Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_EMPTY : TX FIFO empty flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : 0
TX FIFO is not empty
1 : 1
TX FIFO is empty
End of enumeration elements list.
TX_FULL : TX FIFO full flag
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : 0
TX FIFO is not full
1 : 1
TX FIFO is full
End of enumeration elements list.
RX_EMPTY : RX FIFO empty flag
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : 0
RX FIFO is not empty
1 : 1
RX FIFO is empty
End of enumeration elements list.
RX_FULL : RX FIFO full flag
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : 0
RX FIFO is not full
1 : 1
RX FIFO is full
End of enumeration elements list.
BUSY : Busy flag
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : Idle
SSPn is idle
1 : Busy
SSPn is transfering
End of enumeration elements list.
TX_HF_EMPTY : TX FIFO half-empty flag
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : Not half-empty
TX FIFO frame number used is less than 4
1 : Half-empty
TX FIFO frame number used is more equal than 4
End of enumeration elements list.
RX_HF_FULL : RX FIFO half-full flag
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : Not half-full
RX FIFO frame number used is less than 4
1 : Half-full
RX FIFO frame number used is more equal than 4
End of enumeration elements list.
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