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I2S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

RIS

IC

FIFO

CLK

STATUS

IE


CTRL

Offset:0x00 I2S Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START MUTE MONO TRS MS FORMAT CLRFIFO DL FIFOTH I2SEN CHLENGTH

START : Start Transmit/Receive
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Stop

Stop transmit/receive

1 : Start

Start transmit/receive

End of enumeration elements list.

MUTE : Mute enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable mute

1 : Enable

Enable mute (I2SSDA output is 0)

End of enumeration elements list.

MONO : Mono/stereo selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Stereo

Stereo mode

1 : Mono

Mono mode

End of enumeration elements list.

TRS : Transmitter/receiver selection
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Transmitter

Transmitter

1 : Receiver

Receiver

End of enumeration elements list.

MS : Master/slave selection
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Master

Master

1 : Slave

Slave

End of enumeration elements list.

FORMAT : I2S format
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : Standard I2S

Standard I2S format

1 : Left-justified

Left-justified format

2 : Right(MSB)-justified

Right(MSB)-justified format

End of enumeration elements list.

CLRFIFO : Clear I2S FIFO
bits : 7 - 14 (8 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Reset FIFO

End of enumeration elements list.

DL : Data length
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : 8

Data length=8 bits

1 : 16

Data length=16 bits

2 : 24

Data length=24 bits

3 : 32

Data length=32 bits

End of enumeration elements list.

FIFOTH : FIFO threshold level
bits : 12 - 26 (15 bit)
access : read-write

Enumeration:

0 : 0

FIFO threshold level=0

1 : 1

FIFO threshold level=1

2 : 2

FIFO threshold level=2

3 : 3

FIFO threshold level=3

4 : 4

FIFO threshold level=4

5 : 5

FIFO threshold level=5

6 : 6

FIFO threshold level=6

7 : 7

FIFO threshold level=7

End of enumeration elements list.

I2SEN : I2S enable
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Disable

Disable I2S

1 : Enable

Enable I2S

End of enumeration elements list.

CHLENGTH : Bit number of single channel
bits : 16 - 36 (21 bit)
access : read-write

Enumeration:

7 : 7

8 bits

8 : 8

9 bits

9 : 9

10 bits

10 : 10

11 bits

11 : 11

12 bits

12 : 12

13 bits

13 : 13

14 bits

14 : 14

15 bits

15 : 15

16 bits

16 : 16

17 bits

17 : 17

18 bits

18 : 18

19 bits

19 : 19

20 bits

20 : 20

21 bits

21 : 21

22 bits

22 : 22

23 bits

23 : 23

24 bits

24 : 24

25 bits

25 : 25

26 bits

26 : 26

27 bits

27 : 27

28 bits

28 : 28

29 bits

29 : 29

30 bits

30 : 30

31 bits

31 : 31

32 bits (Max)

End of enumeration elements list.


RIS

Offset:0x10 I2S Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOUDIF FIFOOVIF FIFOTHIF

FIFOUDIF : FIFO underflow interrupt flag
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

0 : No FIFO underflow

No FIFO underflow

1 : FIFO underflow

FIFO underflow

End of enumeration elements list.

FIFOOVIF : FIFO overflow interrupt flag
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : No FIFO overflow

No FIFO overflow

1 : FIFO overflow

FIFO overflow

End of enumeration elements list.

FIFOTHIF : FIFO threshold interrupt flag
bits : 6 - 12 (7 bit)
access : read-only

Enumeration:

0 : No FIFO threshold interrupt

No FIFO threshold interrupt

1 : FIFO threshold triggered

FIFO threshold interrupt

End of enumeration elements list.


IC

Offset:0x14 I2S Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IC IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOUDIC FIFOOVIC FIFOTHIC

FIFOUDIC : FIFO underflow interrupt clear
bits : 4 - 8 (5 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear FIFOUDIF bit

End of enumeration elements list.

FIFOOVIC : FIFO overflow interrupt clear
bits : 5 - 10 (6 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear FIFOOVIF bit

End of enumeration elements list.

FIFOTHIC : FIFO threshold interrupt clear
bits : 6 - 12 (7 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear FIFOTHIF bit

End of enumeration elements list.


FIFO

Offset:0x18 I2S FIFO Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLK

Offset:0x04 I2S Clock Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCLKDIV MCLKOEN MCLKSEL BCLKDIV

MCLKDIV : MCLK divider
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : 0

MCLK=MCLK source

1 : 1

MCLK=MCLK source/2

2 : 2

MCLK=MCLK source/4

3 : 3

MCLK=MCLK source/6

4 : 4

MCLK=MCLK source/8

5 : 5

MCLK=MCLK source/10

6 : 6

MCLK=MCLK source/12

7 : 7

MCLK=MCLK source/14

End of enumeration elements list.

MCLKOEN : MLCK output enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable MCLK output

1 : Enable

Enable MCLK output

End of enumeration elements list.

MCLKSEL : MLCK source selection
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : I2S_PCLK

MCLK source of master is from I2S_PCLK

1 : GPIO

MCLK source of master is from GPIO

End of enumeration elements list.

BCLKDIV : BCLK divider
bits : 8 - 23 (16 bit)
access : read-write


STATUS

Offset:0x08 I2S Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SINT RIGHTCH FIFOTHF FIFOFULL FIFOEMPTY FIFOLV

I2SINT : I2S interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No

No I2S interrupt

1 : I2S interrupt occurs

I2S interrupt occurs

End of enumeration elements list.

RIGHTCH : Current channel status
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : Left

Current channel is left channel

1 : Right

Current channel is right channel

End of enumeration elements list.

FIFOTHF : FIFO threshold flag
bits : 6 - 12 (7 bit)
access : read-only

Enumeration:

0 : 0

FIFOLV is larger equal than FIFOTH as transmitter, FIFOLV is less equal than FIFOTH as receiver

1 : 1

FIFOLV is less than FIFOTH as transmitter, FIFOLV is larger than FIFOTH as receiver

End of enumeration elements list.

FIFOFULL : FIFO full flag
bits : 10 - 20 (11 bit)
access : read-only

Enumeration:

0 : Not full

FIFO is not full

1 : Full

FIFO is full

End of enumeration elements list.

FIFOEMPTY : FIFO empty flag
bits : 11 - 22 (12 bit)
access : read-only

Enumeration:

0 : Not empty

FIFO is not empty

1 : Empty

FIFO is empty

End of enumeration elements list.

FIFOLV : FIFO used level
bits : 12 - 27 (16 bit)
access : read-only

Enumeration:

0 : 0

0/8 FIFO is used (Empty)

1 : 1

1/8 FIFO is used

2 : 2

2/8 FIFO is used (Empty)

3 : 3

3/8 FIFO is used

4 : 4

4/8 FIFO is used (Empty)

5 : 5

5/8 FIFO is used

6 : 6

6/8 FIFO is used (Empty)

7 : 7

7/8 FIFO is used

8 : 8

8/8 FIFO is used (Full)

End of enumeration elements list.


IE

Offset:0x0C I2S Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOUDFIEN FIFOOVFIEN FIFOTHIEN

FIFOUDFIEN : FIFO underflow interrupt enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disable FIFO underflow interrupt

1 : Enable

Enable FIFO underflow interrupt

End of enumeration elements list.

FIFOOVFIEN : FIFO overflow interrupt enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

Disable FIFO overflow interrupt

1 : Enable

Enable FIFO overflow interrupt

End of enumeration elements list.

FIFOTHIEN : FIFO threshold interrupt enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Disable FIFO threshold interrupt

1 : Enable

Enable FIFO threshold interrupt

End of enumeration elements list.



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