\n
address_offset : 0x0 Bytes (0x0)
    size : 0x2000 byte (0x0)
    mem_usage : registers
    protection : not protected
    
    Offset:0x00 AHB Clock Enable Register
    address_offset : 0x0 Bytes (0x0)
    size : 32 bit
    access : read-write
    reset_value : 0x0
    reset_Mask : 0x0
    
P0CLKEN : Enable AHB clock for P0
    bits : 0 - 0 (1 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
P1CLKEN : Enable AHB clock for P1
    bits : 1 - 2 (2 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
P2CLKEN : Enable AHB clock for P2
    bits : 2 - 4 (3 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
P3CLKEN : Enable AHB clock for P3
    bits : 3 - 6 (4 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
CT16B0CLKEN : Enable AHB clock for CT16B0
    bits : 6 - 12 (7 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
CT16B1CLKEN : Enable AHB clock for CT16B1
    bits : 7 - 14 (8 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
ADCCLKEN : Enable AHB clock for ADC
    bits : 11 - 22 (12 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
SPI0CLKEN : Enable AHB clock for SPI0
    bits : 12 - 24 (13 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
UART0CLKEN : Enable AHB clock for UART0
    bits : 16 - 32 (17 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
UART1CLKEN : Enable AHB clock for UART1
    bits : 17 - 34 (18 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
UART2CLKEN : Enable AHB clock for UART2
    bits : 18 - 36 (19 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
I2C0CLKEN : Enable AHB clock for I2C0
    bits : 21 - 42 (22 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
WDTCLKEN : Enable AHB clock for WDT
    bits : 24 - 48 (25 bit)
    access : read-write
 Enumeration: 
 0 : Disable 
    
 Disable 
 1 : Enable 
    
 Enable 
End of enumeration elements list.
CLKOUTSEL : Clock output source selection
    bits : 28 - 58 (31 bit)
    access : read-write
 Enumeration: 
 0 : 000 
    
 Disable 
 1 : 001 
    
 ILRC 
 4 : 100 
    
 HCLK 
 5 : 101 
    
 IHRC 
End of enumeration elements list.
    Offset:0x08 APB Clock Prescale Register 1
    address_offset : 0x8 Bytes (0x0)
    size : 32 bit
    access : read-write
    reset_value : 0x0
    reset_Mask : 0x0
    
WDTPRE : WDT APB clock source prescaler
    bits : 20 - 42 (23 bit)
    access : read-write
 Enumeration: 
 0 : 000 
    
 WDT_PCLK = WDT clock source/1 
 1 : 001 
    
 WDT_PCLK = WDT clock source/2 
 2 : 010 
    
 WDT_PCLK = WDT clock source/4 
 3 : 011 
    
 WDT_PCLK = WDT clock source/8 
 4 : 100 
    
 WDT_PCLK = WDT clock source/16 
 5 : 101 
    
 WDT_PCLK = WDT clock source/32 
End of enumeration elements list.
CLKOUTPRE : CLKOUT APB clock source prescaler
    bits : 28 - 58 (31 bit)
    access : read-write
 Enumeration: 
 0 : 000 
    
 FCLKOUT/1 
 1 : 001 
    
 FCLKOUT/2 
 2 : 010 
    
 FCLKOUT/4 
 3 : 011 
    
 FCLKOUT/8 
 4 : 100 
    
 FCLKOUT/16 
 5 : 101 
    
 FCLKOUT/32 
 6 : 110 
    
 FCLKOUT/64 
 7 : 111 
    
 FCLKOUT/128 
End of enumeration elements list.
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