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TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TMRCTRL

CNTCTRL

MCTRL

MR0

TC

PRE

CAPCTRL

CAP0

RIS

IC

PC


TMRCTRL

Offset:0x00 CT16Bn Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMRCTRL TMRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CRST

CEN : Counter enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable counter

1 : Enable

Enable Timer Counter and Prescale Counter for counting

End of enumeration elements list.

CRST : Counter Reset
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Reset Counter

Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK

End of enumeration elements list.


CNTCTRL

Offset:0x10 CT16Bn Counter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCTRL CNTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTM CIS

CTM : Counter/Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : Timer Mode

Every rising PCLK edge

3 : Counter Mode

TC is incremented on both edges on the CAP0 input selected by CIS bits.

3 : Counter Mode

TC is incremented on both edges on the CAP0 input selected by CIS bits.

3 : Counter Mode

TC is incremented on both edges on the CAP0 input selected by CIS bits.

End of enumeration elements list.

CIS : Counter Input Select
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : CT16Bn_CAP0

CT16Bn_CAP0

End of enumeration elements list.


MCTRL

Offset:0x14 CT16Bn Match Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTRL MCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IE MR0RST MR0STOP

MR0IE : Enable generating an interrupt when MR0 matches TC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR0 matches TC

End of enumeration elements list.

MR0RST : Enable reset TC when MR0 matches TC
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR0 matches TC

End of enumeration elements list.

MR0STOP : Stop TC and PC and clear CEN bit when MR0 matches TC
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR0 matches TC

End of enumeration elements list.


MR0

Offset:0x20 CT16Bn MR0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR0 MR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TC

Offset:0x04 CT16Bn Timer Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC

TC : Timer Counter
bits : 0 - 15 (16 bit)
access : read-write


PRE

Offset:0x08 CT16Bn Prescale Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE PRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE

PRE : Prescaler
bits : 0 - 7 (8 bit)
access : read-write


CAPCTRL

Offset:0x80 CT16Bn Capture Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCTRL CAPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0RE CAP0FE CAP0IE CAP0EN

CAP0RE : Capture on CT16Bn_CAP0 rising edge
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.

End of enumeration elements list.

CAP0FE : Capture on CT16Bn_CAP0 falling edge
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.

End of enumeration elements list.

CAP0IE : Interrupt on CT16Bn_CAP0 event
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.

End of enumeration elements list.

CAP0EN : CAP0 function enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Enable CAP0 function

End of enumeration elements list.


CAP0

Offset:0x84 CT16Bn CAP0 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP0 CAP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0

CAP0 : Timer counter capture value
bits : 0 - 15 (16 bit)
access : read-only


RIS

Offset:0xA4 CT16Bn Raw Interrupt Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IF CAP0IF

MR0IF : Match channel 0 interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 0

1 : Met interrupt requirements

Interrupt requirements met on match channel 0

End of enumeration elements list.

CAP0IF : Interrupt flag for capture channel 0
bits : 25 - 50 (26 bit)
access : read-only

Enumeration:

0 : No

No interrupt on CAP0

1 : Met interrupt requirements

Interrupt requirements met on CAP0

End of enumeration elements list.


IC

Offset:0xA8 CT16Bn Interrupt Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IC IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IC CAP0IC

MR0IC : MR0IF clear bit
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR0IF

End of enumeration elements list.

CAP0IC : CAP0IF clear bit
bits : 25 - 50 (26 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CAP0IF

End of enumeration elements list.


PC

Offset:0x0C CT16Bn Prescale Counter Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC

PC : Prescaler Counter
bits : 0 - 7 (8 bit)
access : read-write



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