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LCD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

FCC

RIS

SEGM0

SEGM1

SEGM2

SEGM3

CTRL1

CCTRL1

CCTRL2


CTRL

Offset:0x00 LCD Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCDENB ITB LCDTYPE BIAS SEGSEL1 SEGSEL2 DUTY LCDCLK LCDRATE DRIVEP

LCDENB : LCD driver enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable LCD

1 : 1

Enable LCD

End of enumeration elements list.

ITB : Internal testing bit
bits : 1 - 2 (2 bit)
access : read-write

LCDTYPE : LCD type control bit
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : R

R-type LCD

1 : 4C

4C-type LCD

2 : 1C

1C-type LCD

End of enumeration elements list.

BIAS : LCD bias selection
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : 0

1/3 bias

1 : 1

1/2 bias

End of enumeration elements list.

SEGSEL1 : SEG12~23 enable bit
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

SEG12~23 are GPIO pins

1 : Enable

SEG12~23 are LCD segment pins

End of enumeration elements list.

SEGSEL2 : SEG24~31 enable bit
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

SEG24~31 are GPIO pins

1 : Enable

SEG24~31 are LCD segment pins

End of enumeration elements list.

DUTY : Duty selection
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

1 : 1

1/2 duty

2 : 2

1/3 duty

3 : 3

1/4 duty

End of enumeration elements list.

LCDCLK : LCD clock source selection
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : ILRC

ILRC is LCD clock source

1 : ELS XTAL

ELS Xtal is LCD clock source

End of enumeration elements list.

LCDRATE : LCD clock rate
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : 0

LCD clock rate=LCD clock source/64

1 : 1

LCD clock rate=LCD clock source/128

End of enumeration elements list.

DRIVEP : LCD panel driving ability
bits : 28 - 57 (30 bit)
access : read-write

Enumeration:

0 : Strong

Large panel

1 : Medium

Medium panel

3 : Low

Smaller panel

End of enumeration elements list.


FCC

Offset:0x10 LCD Frame Counter Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCC FCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCENB FCT FCIE

FCENB : LCD frame counter enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable LCD frame counter

1 : 1

Enable LCD frame counter

End of enumeration elements list.

FCT : LCD frame counter threshold value
bits : 1 - 7 (7 bit)
access : read-write

FCIE : LCD frame interrupt enable bit
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : 0

Disable LCD frame interrupt

1 : 1

Enable LCD frame interrupt

End of enumeration elements list.


RIS

Offset:0x14 LCD Raw Interrupt Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCIF

FCIF : LCD frame interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

No interrupt

1 : 1

FC interrupt requirements met

End of enumeration elements list.


SEGM0

Offset:0x20 LCD SEG Memory register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGM0 SEGM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7

SEG0 : SEG0 data for COM0~COM3
bits : 0 - 3 (4 bit)
access : read-write

SEG1 : SEG1 data for COM0~COM3
bits : 4 - 11 (8 bit)
access : read-write

SEG2 : SEG2 data for COM0~COM3
bits : 8 - 19 (12 bit)
access : read-write

SEG3 : SEG3 data for COM0~COM3
bits : 12 - 27 (16 bit)
access : read-write

SEG4 : SEG4 data for COM0~COM3
bits : 16 - 35 (20 bit)
access : read-write

SEG5 : SEG5 data for COM0~COM3
bits : 20 - 43 (24 bit)
access : read-write

SEG6 : SEG6 data for COM0~COM3
bits : 24 - 51 (28 bit)
access : read-write

SEG7 : SEG7 data for COM0~COM3
bits : 28 - 59 (32 bit)
access : read-write


SEGM1

Offset:0x24 LCD SEG Memory register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGM1 SEGM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15

SEG8 : SEG8 data for COM0~COM3
bits : 0 - 3 (4 bit)
access : read-write

SEG9 : SEG9 data for COM0~COM3
bits : 4 - 11 (8 bit)
access : read-write

SEG10 : SEG10 data for COM0~COM3
bits : 8 - 19 (12 bit)
access : read-write

SEG11 : SEG11 data for COM0~COM3
bits : 12 - 27 (16 bit)
access : read-write

SEG12 : SEG12 data for COM0~COM3
bits : 16 - 35 (20 bit)
access : read-write

SEG13 : SEG13 data for COM0~COM3
bits : 20 - 43 (24 bit)
access : read-write

SEG14 : SEG14 data for COM0~COM3
bits : 24 - 51 (28 bit)
access : read-write

SEG15 : SEG15 data for COM0~COM3
bits : 28 - 59 (32 bit)
access : read-write


SEGM2

Offset:0x28 LCD SEG Memory register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGM2 SEGM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23

SEG16 : SEG16 data for COM0~COM3
bits : 0 - 3 (4 bit)
access : read-write

SEG17 : SEG17 data for COM0~COM3
bits : 4 - 11 (8 bit)
access : read-write

SEG18 : SEG18 data for COM0~COM3
bits : 8 - 19 (12 bit)
access : read-write

SEG19 : SEG19 data for COM0~COM3
bits : 12 - 27 (16 bit)
access : read-write

SEG20 : SEG20 data for COM0~COM3
bits : 16 - 35 (20 bit)
access : read-write

SEG21 : SEG21 data for COM0~COM3
bits : 20 - 43 (24 bit)
access : read-write

SEG22 : SEG22 data for COM0~COM3
bits : 24 - 51 (28 bit)
access : read-write

SEG23 : SEG23 data for COM0~COM3
bits : 28 - 59 (32 bit)
access : read-write


SEGM3

Offset:0x2C LCD SEG Memory register 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGM3 SEGM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31

SEG24 : SEG24 data for COM0~COM3
bits : 0 - 3 (4 bit)
access : read-write

SEG25 : SEG25 data for COM0~COM3
bits : 4 - 11 (8 bit)
access : read-write

SEG26 : SEG26 data for COM0~COM3
bits : 8 - 19 (12 bit)
access : read-write

SEG27 : SEG27 data for COM0~COM3
bits : 12 - 27 (16 bit)
access : read-write

SEG28 : SEG28 data for COM0~COM3
bits : 16 - 35 (20 bit)
access : read-write

SEG29 : SEG29 data for COM0~COM3
bits : 20 - 43 (24 bit)
access : read-write

SEG30 : SEG30 data for COM0~COM3
bits : 24 - 51 (28 bit)
access : read-write

SEG31 : SEG31 data for COM0~COM3
bits : 28 - 59 (32 bit)
access : read-write


CTRL1

Offset:0x04 LCD Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCDBNK REF ITB

LCDBNK : LCD blank control bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Normal

Normal display

1 : Blank

All LCD dots Off

End of enumeration elements list.

REF : Resistance selection for LCD Bias Voltage-division
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0 : 0

400K

1 : 1

200K

2 : 2

100K

3 : 3

35K

End of enumeration elements list.

ITB : Internal testing bit
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : 0

Only value 0 is allowed

End of enumeration elements list.


CCTRL1

Offset:0x08 LCD C-Type Control register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTRL1 CCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCP IT2 IT1

VCP : C-Type VLCD output voltage
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0

VLCD=2.70V

1 : 1

VLCD=2.80V

2 : 2

VLCD=2.90V

3 : 3

VLCD=3.00V

4 : 4

1C: VLCD=3.10V, 4C: VLCD=3.06V

5 : 5

1C: VLCD=3.20V, 4C: VLCD=3.14V

6 : 6

1C: VLCD=3.30V, 4C: VLCD=3.20V

7 : 7

1C: VLCD=3.40V, 4C: VLCD=3.30V

8 : 8

1C: N/A, 4C: VLCD=3.40V

9 : 9

1C: N/A, 4C: VLCD=3.60V

10 : 10

1C: N/A, 4C: VLCD=3.80V

11 : 11

1C: N/A, 4C: VLCD=4.00V

12 : 12

1C: N/A, 4C: VLCD=4.20V

13 : 13

1C: N/A, 4C: VLCD=4.40V

14 : 14

1C: N/A, 4C: VLCD=4.70V

15 : 15

1C: N/A, 4C: VLCD=5.00V

End of enumeration elements list.

IT2 : Internal testing bits
bits : 26 - 53 (28 bit)
access : read-write

IT1 : Internal testing bits
bits : 28 - 57 (30 bit)
access : read-write


CCTRL2

Offset:0x0C LCD C-Type Control register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTRL2 CCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IT

IT : Internal testing bits
bits : 1 - 4 (4 bit)
access : read-write



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