Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 Analog Block Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IHRCEN : IHRC enable
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable IHRC
1 : IHRC 12MHz
Enable IHRC 12MHz for HCLK
2 : IHRC 24MHz
Enable IHRC 24MHz for HCLK
4 : IHRC 48MHz
Enable IHRC 48MHz for HCLK
End of enumeration elements list.
Offset:0x10 AHB Clock Prescale Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHBPRE : AHB clock source prescaler
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : 000b
FAHB=FSYSCLK/1
1 : 001b
FAHB=FSYSCLK/2
2 : 010b
FAHB=FSYSCLK/4
3 : 011b
FAHB=FSYSCLK/8
4 : 100b
FAHB=FSYSCLK/16
5 : 101b
FAHB=FSYSCLK/32
6 : 110b
FAHB=FSYSCLK/64
7 : 111b
FAHB=FSYSCLK/128
End of enumeration elements list.
DIV1P5 : SYSCLK prescaler
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : DIV1
SYSCLK = SYSCLK/1
1 : DIV1P5
SYSCLK = SYSCLK/1.5
End of enumeration elements list.
Offset:0x14 System Reset Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRSTF : Software reset flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
No SW reset occurred
1 : 1
SW reset occurred
End of enumeration elements list.
WDTRSTF : WDT reset flag
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
No WDT reset occurred
1 : 1
WDT reset occurred
End of enumeration elements list.
LVDRSTF : LVD reset flag
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
No LVD reset occurred
1 : 1
LVD reset occurred
End of enumeration elements list.
EXTRSTF : External reset flag
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
No Extenral reset occurred
1 : 1
External reset occurred
End of enumeration elements list.
PORRSTF : POR reset flag
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : 0
No POR occurred
1 : 1
POR occurred
End of enumeration elements list.
Offset:0x18 LVD Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDRSTLVL : LVD reset level
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
3 : 2.70V
LVD reset threshold is 2.70V
4 : 3.00V
LVD reset threshold is 3.00V
5 : 3.60V
LVD reset threshold is 3.60V
End of enumeration elements list.
LVDINTLVL : LVD interrupt level
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
3 : 2.70V
LVD interrupt threshold is 2.70V
4 : 3.00V
LVD interrupt threshold is 3.00V
5 : 3.60V
LVD interrupt threshold is 3.60V
End of enumeration elements list.
LVDRSTEN : LVD Reset enable
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : Diable
Disable LVD reset
1 : Enable
Enable LVD reset
End of enumeration elements list.
LVDEN : LVD enable
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : Diable
Disable LVD
1 : Enable
Enable LVD
End of enumeration elements list.
Offset:0x1C External Reset Pin Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESETDIS : External reset pin disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Enable
P0.7 acts as nRESET pin
1 : Disable
P0.7 acts as GPIO pin
End of enumeration elements list.
Offset:0x20 SWD Pin Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWDDIS : SWD pin disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Enable
Enable SWD pins
1 : Disable
Disable SWD pins
End of enumeration elements list.
Offset:0x34 IHRC Frequency Adjustment register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADJEN : IHRC frequency adjustment enable bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable
1 : Enable
Enable
End of enumeration elements list.
DIR : IHRC frequency adjusting direction bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Positive
Positive
1 : Negative
Negative
End of enumeration elements list.
ADJ : IHRC frequency adjusting bits
bits : 4 - 15 (12 bit)
access : read-write
SYSKEY : System register key
bits : 16 - 47 (32 bit)
access : write-only
Offset:0x08 Clock Source Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IHRCRDY : IHRC ready flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : 0
IHRC is Not Ready
1 : 1
IHRC is Ready
End of enumeration elements list.
Offset:0x0C System Clock Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLKSEL : System clock source selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IHRC
HCLK=IHRC
1 : ILRC
HCLK=ILRC
End of enumeration elements list.
SYSCLKST : System clock switch status
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : IHRC
IHRC is used as system clock
1 : ILRC
ILRC is used as system clock
End of enumeration elements list.
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