Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 GPIO Port n Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data of Pn.0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Pn.0 is 0
1 : 1
Pn.0 is 1
End of enumeration elements list.
DATA1 : Data of Pn.1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
Pn.1 is 0
1 : 1
Pn.1 is 1
End of enumeration elements list.
DATA2 : Data of Pn.2
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
Pn.2 is 0
1 : 1
Pn.2 is 1
End of enumeration elements list.
DATA3 : Data of Pn.3
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
Pn.3 is 0
1 : 1
Pn.3 is 1
End of enumeration elements list.
DATA4 : Data of Pn.4
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : 0
Pn.4 is 0
1 : 1
Pn.4 is 1
End of enumeration elements list.
DATA5 : Data of Pn.5
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : 0
Pn.5 is 0
1 : 1
Pn.5 is 1
End of enumeration elements list.
DATA6 : Data of Pn.6
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : 0
Pn.6 is 0
1 : 1
Pn.6 is 1
End of enumeration elements list.
DATA7 : Data of Pn.7
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : 0
Pn.7 is 0
1 : 1
Pn.7 is 1
End of enumeration elements list.
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBS0 : Interrupt on Pn.0 is triggered ob both edges
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.0 trigger an interrupt
End of enumeration elements list.
IBS1 : Interrupt on Pn.1 is triggered ob both edges
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.1 trigger an interrupt
End of enumeration elements list.
IBS2 : Interrupt on Pn.2 is triggered ob both edges
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.2 trigger an interrupt
End of enumeration elements list.
IBS3 : Interrupt on Pn.3 is triggered ob both edges
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.3 trigger an interrupt
End of enumeration elements list.
IBS4 : Interrupt on Pn.4 is triggered ob both edges
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.4 trigger an interrupt
End of enumeration elements list.
IBS5 : Interrupt on Pn.5 is triggered ob both edges
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.5 trigger an interrupt
End of enumeration elements list.
IBS6 : Interrupt on Pn.6 is triggered ob both edges
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.6 trigger an interrupt
End of enumeration elements list.
IBS7 : Interrupt on Pn.7 is triggered ob both edges
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
1 : Both edge
Both edges on Pn.7 trigger an interrupt
End of enumeration elements list.
Offset:0x14 GPIO Port n Interrupt Event Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEV0 : Interrupt trigged evnet on Pn.0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.0 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.0 triggers an interrupt
End of enumeration elements list.
IEV1 : Interrupt trigged evnet on Pn.1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.1 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.1 triggers an interrupt
End of enumeration elements list.
IEV2 : Interrupt trigged evnet on Pn.2
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.2 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.2 triggers an interrupt
End of enumeration elements list.
IEV3 : Interrupt trigged evnet on Pn.3
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.3 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.3 triggers an interrupt
End of enumeration elements list.
IEV4 : Interrupt trigged evnet on Pn.4
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.4 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.4 triggers an interrupt
End of enumeration elements list.
IEV5 : Interrupt trigged evnet on Pn.5
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.5 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.5 triggers an interrupt
End of enumeration elements list.
IEV6 : Interrupt trigged evnet on Pn.6
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.6 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.6 triggers an interrupt
End of enumeration elements list.
IEV7 : Interrupt trigged evnet on Pn.7
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : 0
Rising edge or High level on Pn.7 triggers an interrupt
1 : 1
Falling edge or Low level on Pn.7 triggers an interrupt
End of enumeration elements list.
Offset:0x18 GPIO Port n Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE0 : Interrupt on Pn.0 enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.0
1 : Enable
Enable interrupt on Pn.0
End of enumeration elements list.
IE1 : Interrupt on Pn.1 enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.1
1 : Enable
Enable interrupt on Pn.1
End of enumeration elements list.
IE2 : Interrupt on Pn.2 enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.2
1 : Enable
Enable interrupt on Pn.2
End of enumeration elements list.
IE3 : Interrupt on Pn.3 enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.3
1 : Enable
Enable interrupt on Pn.3
End of enumeration elements list.
IE4 : Interrupt on Pn.4 enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.4
1 : Enable
Enable interrupt on Pn.4
End of enumeration elements list.
IE5 : Interrupt on Pn.5 enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.5
1 : Enable
Enable interrupt on Pn.5
End of enumeration elements list.
IE6 : Interrupt on Pn.6 enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.6
1 : Enable
Enable interrupt on Pn.6
End of enumeration elements list.
IE7 : Interrupt on Pn.7 enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Disable interrupt on Pn.7
1 : Enable
Enable interrupt on Pn.7
End of enumeration elements list.
Offset:0x1C GPIO Port n Raw Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IF0 : Pn.0 raw interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.0
1 : 1
Interrupt requirements met on Pn.0
End of enumeration elements list.
IF1 : Pn.1 raw interrupt flag
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.1
1 : 1
Interrupt requirements met on Pn.1
End of enumeration elements list.
IF2 : Pn.2 raw interrupt flag
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.2
1 : 1
Interrupt requirements met on Pn.2
End of enumeration elements list.
IF3 : Pn.3 raw interrupt flag
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.3
1 : 1
Interrupt requirements met on Pn.3
End of enumeration elements list.
IF4 : Pn.4 raw interrupt flag
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.4
1 : 1
Interrupt requirements met on Pn.4
End of enumeration elements list.
IF5 : Pn.5 raw interrupt flag
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.5
1 : 1
Interrupt requirements met on Pn.5
End of enumeration elements list.
IF6 : Pn.6 raw interrupt flag
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.6
1 : 1
Interrupt requirements met on Pn.6
End of enumeration elements list.
IF7 : Pn.7 raw interrupt flag
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : 0
No interrupt on Pn.7
1 : 1
Interrupt requirements met on Pn.7
End of enumeration elements list.
Offset:0x20 GPIO Port n Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IC0 : Pn.0 interrupt flag clear
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.0
End of enumeration elements list.
IC1 : Pn.1 interrupt flag clear
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.1
End of enumeration elements list.
IC2 : Pn.2 interrupt flag clear
bits : 2 - 4 (3 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.2
End of enumeration elements list.
IC3 : Pn.3 interrupt flag clear
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.3
End of enumeration elements list.
IC4 : Pn.4 interrupt flag clear
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.4
End of enumeration elements list.
IC5 : Pn.5 interrupt flag clear
bits : 5 - 10 (6 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.5
End of enumeration elements list.
IC6 : Pn.6 interrupt flag clear
bits : 6 - 12 (7 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.6
End of enumeration elements list.
IC7 : Pn.7 interrupt flag clear
bits : 7 - 14 (8 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear interrupt flag on Pn.7
End of enumeration elements list.
Offset:0x24 GPIO Port n Bits Set Operation Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BSET0 : Set Pn.0
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.0 to 1
End of enumeration elements list.
BSET1 : Set Pn.1
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.1 to 1
End of enumeration elements list.
BSET2 : Set Pn.2
bits : 2 - 4 (3 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.2 to 1
End of enumeration elements list.
BSET3 : Set Pn.3
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.3 to 1
End of enumeration elements list.
BSET4 : Set Pn.4
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.4 to 1
End of enumeration elements list.
BSET5 : Set Pn.5
bits : 5 - 10 (6 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.5 to 1
End of enumeration elements list.
BSET6 : Set Pn.6
bits : 6 - 12 (7 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.6 to 1
End of enumeration elements list.
BSET7 : Set Pn.7
bits : 7 - 14 (8 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Set
Set Pn.7 to 1
End of enumeration elements list.
Offset:0x28 GPIO Port n Bits Clear Operation Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BCLR0 : Clear Pn.0
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.0
End of enumeration elements list.
BCLR1 : Clear Pn.1
bits : 1 - 2 (2 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.1
End of enumeration elements list.
BCLR2 : Clear Pn.2
bits : 2 - 4 (3 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.2
End of enumeration elements list.
BCLR3 : Clear Pn.3
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.3
End of enumeration elements list.
BCLR4 : Clear Pn.4
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.4
End of enumeration elements list.
BCLR5 : Clear Pn.5
bits : 5 - 10 (6 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.5
End of enumeration elements list.
BCLR6 : Clear Pn.6
bits : 6 - 12 (7 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.6
End of enumeration elements list.
BCLR7 : Clear Pn.7
bits : 7 - 14 (8 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear Pn.7
End of enumeration elements list.
Offset:0x04 GPIO Port n Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE0 : Mode of Pn.0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : I
Pn.0 is Input pin
1 : O
Pn.0 is Output pin
End of enumeration elements list.
MODE1 : Mode of Pn.1
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : I
Pn.1 is Input pin
1 : O
Pn.1 is Output pin
End of enumeration elements list.
MODE2 : Mode of Pn.2
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : I
Pn.2 is Input pin
1 : O
Pn.2 is Output pin
End of enumeration elements list.
MODE3 : Mode of Pn.3
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : I
Pn.3 is Input pin
1 : O
Pn.3 is Output pin
End of enumeration elements list.
MODE4 : Mode of Pn.4
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : I
Pn.4 is Input pin
1 : O
Pn.4 is Output pin
End of enumeration elements list.
MODE5 : Mode of Pn.5
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : I
Pn.5 is Input pin
1 : O
Pn.5 is Output pin
End of enumeration elements list.
MODE6 : Mode of Pn.6
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : I
Pn.6 is Input pin
1 : O
Pn.6 is Output pin
End of enumeration elements list.
MODE7 : Mode of Pn.7
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : I
Pn.7 is Input pin
1 : O
Pn.7 is Output pin
End of enumeration elements list.
Offset:0x08 GPIO Port n Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFG0 : Configuration of Pn.0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG1 : Configuration of Pn.1
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG2 : Configuration of Pn.2
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG3 : Configuration of Pn.3
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG4 : Configuration of Pn.4
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG5 : Configuration of Pn.5
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG6 : Configuration of Pn.6
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
CFG7 : Configuration of Pn.7
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
0 : 00b
Enable pull-up resistor
2 : 10b
Inactive (schmitt trigger enabled)
3 : 11b
Inactive (schmitt trigger disabled)
End of enumeration elements list.
Offset:0x0C GPIO Port n Interrupt Sense Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IS0 : Interrupt on Pn.0 is event or edge sensitive
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.0 is edge sensitive
1 : Event
Interrupt on Pn.0 is event sensitive
End of enumeration elements list.
IS1 : Interrupt on Pn.1 is event or edge sensitive
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.1 is edge sensitive
1 : Event
Interrupt on Pn.1 is event sensitive
End of enumeration elements list.
IS2 : Interrupt on Pn.2 is event or edge sensitive
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.2 is edge sensitive
1 : Event
Interrupt on Pn.2 is event sensitive
End of enumeration elements list.
IS3 : Interrupt on Pn.3 is event or edge sensitive
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.3 is edge sensitive
1 : Event
Interrupt on Pn.3 is event sensitive
End of enumeration elements list.
IS4 : Interrupt on Pn.4 is event or edge sensitive
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.4 is edge sensitive
1 : Event
Interrupt on Pn.4 is event sensitive
End of enumeration elements list.
IS5 : Interrupt on Pn.5 is event or edge sensitive
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.5 is edge sensitive
1 : Event
Interrupt on Pn.5 is event sensitive
End of enumeration elements list.
IS6 : Interrupt on Pn.6 is event or edge sensitive
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.6 is edge sensitive
1 : Event
Interrupt on Pn.6 is event sensitive
End of enumeration elements list.
IS7 : Interrupt on Pn.7 is event or edge sensitive
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Edge
Interrupt on Pn.7 is edge sensitive
1 : Event
Interrupt on Pn.7 is event sensitive
End of enumeration elements list.
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