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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADM

RIS

ADB

IE


ADM

Offset:0x00 ADC Management Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM ADM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS GCHS EOC ADS ADLEN ADCKS ADENB AVREFHSEL VHS

CHS : ADC input channel
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : 0

AIN0

1 : 1

AIN1

2 : 2

AIN2

3 : 3

AIN3

4 : 4

AIN4

5 : 5

AIN5(Internal reference voltage 4.5V/3V/2V)

6 : 6

VDD

7 : 7

VSS

End of enumeration elements list.

GCHS : ADC global channel enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN channel

1 : Enable

Enable AIN channel

End of enumeration elements list.

EOC : ADC status
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Busy

ADC processing

1 : End

End of conversion

End of enumeration elements list.

ADS : ADC start control
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Stop

ADC stopped

1 : Start

Start ADC conversion

End of enumeration elements list.

ADLEN : ADC resolution
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : 8-bit

8-bit ADB

1 : 12-bit

12-bit ADB

End of enumeration elements list.

ADCKS : ADC clock source divider
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

0 : 000b

ADC_PCLK/1

1 : 001b

ADC_PCLK/2

2 : 010b

ADC_PCLK/4

3 : 011b

ADC_PCLK/8

5 : 101b

ADC_PCLK/16

6 : 110b

ADC_PCLK/32

End of enumeration elements list.

ADENB : ADC enable
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : Disable

Disable ADC

1 : Enable

Enable ADC

End of enumeration elements list.

AVREFHSEL : ADC high reference voltage source
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : Interal Ref. Voltage

P2.0 acts as GPIO or AIN0 pin

1 : External reference voltage

P2.0 acts as AVREFH pin

End of enumeration elements list.

VHS : Internal Ref. voltage source
bits : 13 - 28 (16 bit)
access : read-write

Enumeration:

0 : 000b

Internal 2.0V as ADC internal reference high voltage

1 : 001b

Internal 3.0V as ADC internal reference high voltage

2 : 010b

Internal 4.5V as ADC internal reference high voltage

4 : 100b

VDD as ADC internal reference high voltage, Internal 2.0V as AIN10

5 : 101b

VDD as ADC internal reference high voltage, Internal 3.0V as AIN10

6 : 110b

VDD as ADC internal reference high voltage, Internal 4.5V as AIN10

7 : 111b

VDD as ADC internal reference high voltage

End of enumeration elements list.


RIS

Offset:0x10 ADC Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOCIF0 EOCIF1 EOCIF2 EOCIF3 EOCIF4 EOCIF5 EOCIF6 EOCIF7

EOCIF0 : AIN0 interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN0

1 : Met interrupt requirements

AIN0 completes ADC conversion

End of enumeration elements list.

EOCIF1 : AIN1 interrupt flag
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN1

1 : Met interrupt requirements

AIN1 completes ADC conversion

End of enumeration elements list.

EOCIF2 : AIN2 interrupt flag
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN2

1 : Met interrupt requirements

AIN2 completes ADC conversion

End of enumeration elements list.

EOCIF3 : AIN0 interrupt flag
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN3

1 : Met interrupt requirements

AIN3 completes ADC conversion

End of enumeration elements list.

EOCIF4 : AIN4 interrupt flag
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN4

1 : Met interrupt requirements

AIN4 completes ADC conversion

End of enumeration elements list.

EOCIF5 : AIN5 interrupt flag
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN5

1 : Met interrupt requirements

AIN5 completes ADC conversion

End of enumeration elements list.

EOCIF6 : AIN6 interrupt flag
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN6

1 : Met interrupt requirements

AIN6 completes ADC conversion

End of enumeration elements list.

EOCIF7 : AIN7 interrupt flag
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : No interrupt

No interrupt on AIN7

1 : Met interrupt requirements

AIN7 completes ADC conversion

End of enumeration elements list.


ADB

Offset:0x04 ADC Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADB ADB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADB

ADB : ADB11~ADB4 bits for 8-bit ADC, ADB11~ADB0 bits for 12-bit ADC
bits : 0 - 11 (12 bit)
access : read-only


IE

Offset:0x0C ADC Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IE0 IE1 IE2 IE3 IE4 IE5 IE6 IE7

IE0 : AIN0 interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN0 interrupt

1 : Enable

ADC interrupt is triggered when AIN0 completes ADC conversion

End of enumeration elements list.

IE1 : AIN1 interrupt enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN1 interrupt

1 : Enable

ADC interrupt is triggered when AIN1 completes ADC conversion

End of enumeration elements list.

IE2 : AIN2 interrupt enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN2 interrupt

1 : Enable

ADC interrupt is triggered when AIN2 completes ADC conversion

End of enumeration elements list.

IE3 : AIN3 interrupt enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN3 interrupt

1 : Enable

ADC interrupt is triggered when AIN3 completes ADC conversion

End of enumeration elements list.

IE4 : AIN4 interrupt enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN4 interrupt

1 : Enable

ADC interrupt is triggered when AIN4 completes ADC conversion

End of enumeration elements list.

IE5 : AIN5 interrupt enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN5 interrupt

1 : Enable

ADC interrupt is triggered when AIN5 completes ADC conversion

End of enumeration elements list.

IE6 : AIN6 interrupt enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN6 interrupt

1 : Enable

ADC interrupt is triggered when AIN6 completes ADC conversion

End of enumeration elements list.

IE7 : AIN7 interrupt enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

Disable AIN7 interrupt

1 : Enable

ADC interrupt is triggered when AIN7 completes ADC conversion

End of enumeration elements list.



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