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CMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

RIS

IC

DB

VIREF

OS

IE


CTRL

Offset:0x00 CMP Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0EN CM0PREF CM0NS CM0RS CM0OEN CM0G

CM0EN : CMP0 Enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP0

1 : Enable

Enable CMP0

End of enumeration elements list.

CM0PREF : CMP0 Positive reference voltage (VPREF0) source
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0 : VIREF0

VIREF0. CM0P0/CM0P1/CM0P2 pins are GPIO mode.

1 : CM0P0

CM0P0 is comparator positive input pin, and isolate GPIO function

2 : CM0P1

CM0P1 is comparator positive input pin, and isolate GPIO function

3 : CM0P2

CM0P2 is comparator positive input pin, and isolate GPIO function

End of enumeration elements list.

CM0NS : CMP0 negative input pin selection bit
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : CM0N0

CM0N0 is comparator negative input pin, and isolate GPIO function

1 : CM0N1

CM0N1 is comparator negative input pin, and isolate GPIO function

2 : CM0N2

CM0N2 is comparator negative input pin, and isolate GPIO function

End of enumeration elements list.

CM0RS : CMP0 internal reference voltage (VIREF0) selection bits
bits : 5 - 13 (9 bit)
access : read-write

Enumeration:

0 : 0000b

VIREF0=VIREF

1 : 0001b

VIREF0=VIREF*1/16

2 : 0010b

VIREF0=VIREF*2/16

3 : 0011b

VIREF0=VIREF*3/16

4 : 0100b

VIREF0=VIREF*4/16

5 : 0101b

VIREF0=VIREF*5/16

6 : 0110b

VIREF0=VIREF*6/16

7 : 0111b

VIREF0=VIREF*7/16

8 : 1000b

VIREF0=VIREF*8/16

9 : 1001b

VIREF0=VIREF*9/16

10 : 1010b

VIREF0=VIREF*10/16

11 : 1011b

VIREF0=VIREF*11/16

12 : 1100b

VIREF0=VIREF*12/16

13 : 1101b

VIREF0=VIREF*13/16

14 : 1110b

VIREF0=VIREF*14/16

15 : 1111b

VIREF0=VIREF*15/16

End of enumeration elements list.

CM0OEN : CMP0 Output pin control bit
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : Disable

Disable CM0O

1 : Enable

Enable CM0O

End of enumeration elements list.

CM0G : CMP0 interrupt trigger direction control bit
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : Falling range trigger

CMP0 output status is from high to low as VPREF0 less than CM0N

1 : Rising edge trigger

CMP0 output status is from low to high as VPREF0 more than CM0N

End of enumeration elements list.


RIS

Offset:0x10 CMP n Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IF

CM0IF : CMP0 raw interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on CMP0

1 : Met interrupt requirements

Interrupt requirements met on CMP0

End of enumeration elements list.


IC

Offset:0x14 CMP Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IC IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IC

CM0IC : CMP0 interrupt flag clear bit
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CMP0 interrupt flag

End of enumeration elements list.


DB

Offset:0x18 CMP Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DB DB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0DB

CM0DB : Count for CMP0 output debounce time
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : 000b

Disable CMP0 output debounce circuit

1 : 001b

CMP0 output debounce time = 2*CMP0_PCLK

2 : 010b

CMP0 output debounce time = 4*CMP0_PCLK

3 : 011b

CMP0 output debounce time = 8*CMP0_PCLK

4 : 100b

CMP0 output debounce time = 16*CMP0_PCLK

5 : 101b

CMP0 output debounce time = 32*CMP0_PCLK

6 : 110b

CMP0 output debounce time = 64*CMP0_PCLK

7 : 111b

CMP0 output debounce time = 128*CMP0_PCLK

End of enumeration elements list.


VIREF

Offset:0x04 CMP Internal Reference Voltage register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VIREF VIREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPIREFEN CMPIREF

CMPIREFEN : CMP internal reference voltage (VIREF) enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP internal reference voltage

1 : Enable

Enable CMP internal reference voltage

End of enumeration elements list.

CMPIREF : CMP internal reference voltage (VIREF) source
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

3 : VDD

VIREF=VDD

2 : Internal 1P5V

VIREF=Internal 1P5V

1 : Internal 2V

VIREF=Internal 2V

0 : Internal 3V

VIREF=Internal 3V

End of enumeration elements list.


OS

Offset:0x08 CMP Output Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OS OS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0OUT

CM0OUT : CMP0 Output flag bit
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : CMP0 positive voltage is less than CM0N voltage

VPREF0 is less than CM0N voltage

1 : CMP0 positive voltage is more than CM0N voltage

VPREF0 is more than CM0N voltage

End of enumeration elements list.


IE

Offset:0x0C CMP Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0IE

CM0IE : CMP0 interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable CMP0 interrupt

1 : Enable

Enable CMP0 interrupt

End of enumeration elements list.



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