\n

TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TMRCTRL

CNTCTRL

MCTRL

MR0

MR1

MR2

MR3

TC

MR9

PRE

CAPCTRL

CAP0

EM

PWMCTRL

RIS

IC

PC


TMRCTRL

Offset:0x00 CT16Bn Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMRCTRL TMRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CRST CLKSEL CM

CEN : Counter enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable counter

1 : Enable

Enable Timer Counter and Prescale Counter for counting

End of enumeration elements list.

CRST : Counter Reset
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Reset Counter

Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK

End of enumeration elements list.

CLKSEL : PCLK source
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : HCLK

CT16Bn PCLK source=HCLK

1 : PLL_VCO

CT16Bn PCLK source=PLL_VCO

2 : ELS Xtal

CT16Bn PCLK source=ELS Xtal

End of enumeration elements list.

CM : Counting mode selection
bits : 4 - 10 (7 bit)
access : read-write

Enumeration:

0 : Up-counting mode

Edge-aligned Up-counting mode

1 : Down-counting mode

Edge-aligned Down-counting mode

2 : Center-aligned counting mode 1

The match interrupt flag is set during the down-counting period

4 : Center-aligned counting mode 2

The match interrupt flag is set during the up-counting period

6 : Center-aligned counting mode 3

The match interrupt flag is set during both up-counting and down-counting period

End of enumeration elements list.


CNTCTRL

Offset:0x10 CT16Bn Counter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCTRL CNTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTM

CTM : Counter/Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : Timer Mode

Timer Mode: every rising PCLK edge

1 : Counter Mode 1

TC is incremented on rising edges on the CAP0 input selected by CIS bits.

2 : Counter Mode 2

TC is incremented on falling edges on the CAP0 input selected by CIS bits.

3 : Counter Mode 3

TC is incremented on both edges on the CAP0 input selected by CIS bits.

End of enumeration elements list.


MCTRL

Offset:0x14 CT16Bn Match Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTRL MCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IE MR0RST MR0STOP MR1IE MR1RST MR1STOP MR2IE MR2RST MR2STOP MR3IE MR3RST MR3STOP MR9IE MR9RST MR9STOP PWMKEY

MR0IE : Enable generating an interrupt when MR0 matches TC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR0 matches TC

End of enumeration elements list.

MR0RST : Enable reset TC when MR0 matches TC
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR0 matches TC

End of enumeration elements list.

MR0STOP : Stop TC and PC and clear CEN bit when MR0 matches TC
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR0 matches TC

End of enumeration elements list.

MR1IE : Enable generating an interrupt when MR1 matches TC
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR1 matches TC

End of enumeration elements list.

MR1RST : Enable reset TC when MR1 matches TC
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR1 matches TC

End of enumeration elements list.

MR1STOP : Stop TC and PC and clear CEN bit when MR1 matches TC
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR1 matches TC

End of enumeration elements list.

MR2IE : Enable generating an interrupt when MR2 matches TC
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR2 matches TC

End of enumeration elements list.

MR2RST : Enable reset TC when MR2 matches TC
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR2 matches TC

End of enumeration elements list.

MR2STOP : Stop TC and PC and clear CEN bit when MR2 matches TC
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR2 matches TC

End of enumeration elements list.

MR3IE : Enable generating an interrupt when MR3 matches TC
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR3 matches TC

End of enumeration elements list.

MR3RST : Enable reset TC when MR3 matches TC
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR3 matches TC

End of enumeration elements list.

MR3STOP : Stop TC and PC and clear CEN bit when MR3 matches TC
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR3 matches TC

End of enumeration elements list.

MR9IE : Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
bits : 21 - 42 (22 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Generating an interrupt when MR9 matches TC

End of enumeration elements list.

MR9RST : Enable reset TC when MR9 matches TC
bits : 22 - 44 (23 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Reset TC when MR9 matches TC

End of enumeration elements list.

MR9STOP : Stop TC and PC and clear CEN bit when MR9 matches TC
bits : 23 - 46 (24 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Stop TC and PC and clear CEN bit when MR9 matches TC

End of enumeration elements list.

PWMKEY : PWM register key.
bits : 24 - 55 (32 bit)
access : write-only


MR0

Offset:0x20 CT16Bn MR0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR0 MR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR PWMKEY

MR : Timer counter match value
bits : 0 - 15 (16 bit)
access : read-write

PWMKEY : PWM register key.
bits : 24 - 55 (32 bit)
access : write-only


MR1

Offset:0x24 CT16Bn MR1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR1 MR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR PWMKEY

MR : Timer counter match value
bits : 0 - 15 (16 bit)
access : read-write

PWMKEY : PWM register key
bits : 24 - 55 (32 bit)
access : write-only


MR2

Offset:0x28 CT16Bn MR2 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR2 MR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR PWMKEY

MR : Timer counter match value
bits : 0 - 15 (16 bit)
access : read-write

PWMKEY : PWM register key
bits : 24 - 55 (32 bit)
access : write-only


MR3

Offset:0x2C CT16Bn MR3 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR3 MR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR PWMKEY

MR : Timer counter match value
bits : 0 - 15 (16 bit)
access : read-write

PWMKEY : PWM register key
bits : 24 - 55 (32 bit)
access : write-only


TC

Offset:0x04 CT16Bn Timer Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC

TC : Timer Counter
bits : 0 - 15 (16 bit)
access : read-write


MR9

Offset:0x44 CT16Bn MR9 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR9 MR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR PWMKEY

MR : Timer counter match value
bits : 0 - 15 (16 bit)
access : read-write

PWMKEY : PWM register key
bits : 24 - 55 (32 bit)
access : write-only


PRE

Offset:0x08 CT16Bn Prescale Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE PRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE

PRE : Prescalzer
bits : 0 - 7 (8 bit)
access : read-write


CAPCTRL

Offset:0x84 CT16Bn Capture Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCTRL CAPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0RE CAP0FE CAP0IE CAP0EN

CAP0RE : Capture/Reset on CT16Bn_CAP0 signal rising edge
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.

End of enumeration elements list.

CAP0FE : Capture/Reset on CT16Bn_CAP0 signal falling edge
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.

End of enumeration elements list.

CAP0IE : Interrupt on CT16Bn_CAP0 event
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.

End of enumeration elements list.

CAP0EN : CAP0 function enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable

1 : Enable

Enable CAP0 function for external Capture pin

End of enumeration elements list.


CAP0

Offset:0x88 CT16Bn CAP0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP0 CAP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0

CAP0 : Timer counter capture value
bits : 0 - 15 (16 bit)
access : read-only


EM

Offset:0x8C CT16Bn External Match Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM EM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EMC0 EMC1 EMC2 EMC3 PWMKEY

EM0 : When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
bits : 0 - 0 (1 bit)
access : read-write

EM1 : When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
bits : 1 - 2 (2 bit)
access : read-write

EM2 : When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
bits : 2 - 4 (3 bit)
access : read-write

EM3 : When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output.
bits : 3 - 6 (4 bit)
access : read-write

EMC0 : CT16Bn_PWM0 functionality
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM0 pin is LOW

2 : High

CT16Bn_PWM0 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM0 pin

End of enumeration elements list.

EMC1 : CT16Bn_PWM1 functionality
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM1 pin is LOW

2 : High

CT16Bn_PWM1 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM1 pin

End of enumeration elements list.

EMC2 : CT16Bn_PWM2 functionality
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM2 pin is LOW

2 : High

CT16Bn_PWM2 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM2 pin

End of enumeration elements list.

EMC3 : CT16Bn_PWM3 functionality
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : Do Nothing

Do nothing

1 : Low

CT16Bn_PWM3 pin is LOW

2 : High

CT16Bn_PWM3 pin is HIGH

3 : Toggle

Toggle CT16Bn_PWM3 pin

End of enumeration elements list.

PWMKEY : PWM register key.
bits : 24 - 55 (32 bit)
access : write-only


PWMCTRL

Offset:0x98 CT16Bn PWM Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMCTRL PWMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0EN PWM1EN PWM2EN PWM3EN PWM0MODE PWM1MODE PWM2MODE PWM3MODE PWM0IOEN PWM1IOEN PWM2IOEN PWM3IOEN PWMKEY

PWM0EN : PWM0 enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM0 is controlled by EM0

1 : Enable

Enable PWM mode for CT16Bn_PWM0

End of enumeration elements list.

PWM1EN : PWM1 enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM1 is controlled by EM1

1 : Enable

Enable PWM mode for CT16Bn_PWM1

End of enumeration elements list.

PWM2EN : PWM2 enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM2 is controlled by EM2

1 : Enable

Enable PWM mode for CT16Bn_PWM2

End of enumeration elements list.

PWM3EN : PWM2 enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM3 is controlled by EM3

1 : Enable

Enable PWM mode for CT16Bn_PWM3

End of enumeration elements list.

PWM0MODE : PWM0 output mode
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM0 is 0 when TC is less than MR0.

1 : PWM mode 2

During up-counting, PWM0 is 1 when TC is less than MR0.

2 : Force 0

PWM0 is forced to 0

3 : Force 1

PWM0 is forced to 1

End of enumeration elements list.

PWM1MODE : PWM1 output mode
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM1 is 0 when TC is less than MR1.

1 : PWM mode 2

During up-counting, PWM1 is 1 when TC is less than MR1.

2 : Force 0

PWM1 is forced to 0

3 : Force 1

PWM1 is forced to 1

End of enumeration elements list.

PWM2MODE : PWM2 output mode
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM2 is 0 when TC is less than MR2.

1 : PWM mode 2

During up-counting, PWM2 is 1 when TC is less than MR2.

2 : Force 0

PWM2 is forced to 0

3 : Force 1

PWM2 is forced to 1

End of enumeration elements list.

PWM3MODE : PWM3 output mode
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : PWM mode 1

During up-counting, PWM3 is 0 when TC is less than MR3.

1 : PWM mode 2

During up-counting, PWM3 is 1 when TC is less than MR3.

2 : Force 0

PWM3 is forced to 0

3 : Force 1

PWM3 is forced to 1

End of enumeration elements list.

PWM0IOEN : CT16Bn_PWM0/GPIO selection
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM0 pin is act as GPIO

1 : Enable

CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit

End of enumeration elements list.

PWM1IOEN : CT16Bn_PWM1/GPIO selection
bits : 21 - 42 (22 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM1 pin is act as GPIO

1 : Enable

CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit

End of enumeration elements list.

PWM2IOEN : CT16Bn_PWM2/GPIO selection
bits : 22 - 44 (23 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM2 pin is act as GPIO

1 : Enable

CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit

End of enumeration elements list.

PWM3IOEN : CT16Bn_PWM3/GPIO selection
bits : 23 - 46 (24 bit)
access : read-write

Enumeration:

0 : Disable

CT16Bn_PWM3 pin is act as GPIO

1 : Enable

CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit

End of enumeration elements list.

PWMKEY : PWM register key.
bits : 24 - 55 (32 bit)
access : write-only


RIS

Offset:0xA8 CT16Bn Raw Interrupt Status Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IF MR1IF MR2IF MR3IF CAP0IF MR9IF

MR0IF : Match channel 0 interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 0

1 : Met interrupt requirements

Interrupt requirements met on match channel 0

End of enumeration elements list.

MR1IF : Match channel 1 interrupt flag
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 1

1 : Met interrupt requirements

Interrupt requirements met on match channel 1

End of enumeration elements list.

MR2IF : Match channel 2 interrupt flag
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 2

1 : Met interrupt requirements

Interrupt requirements met on match channel 2

End of enumeration elements list.

MR3IF : Match channel 3 interrupt flag
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 3

1 : Met interrupt requirements

Interrupt requirements met on match channel 3

End of enumeration elements list.

CAP0IF : Capture channel 0 interrupt flag
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

0 : No

No interrupt on CAP0

1 : Met interrupt requirements

Interrupt requirements met on CAP0

End of enumeration elements list.

MR9IF : Match channel 9 interrupt flag
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : No interrupt

No interrupt on match channel 9

1 : Met interrupt requirements

Interrupt requirements met on match channel 9

End of enumeration elements list.


IC

Offset:0xAC CT16Bn Interrupt Clear Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IC IC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0IC MR1IC MR2IC MR3IC CAP0IC MR9IC

MR0IC : MR0IF clear bit
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR0IF

End of enumeration elements list.

MR1IC : MR1IF clear bit
bits : 1 - 2 (2 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR1IF

End of enumeration elements list.

MR2IC : MR2IF clear bit
bits : 2 - 4 (3 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR2IF

End of enumeration elements list.

MR3IC : MR3IF clear bit
bits : 3 - 6 (4 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR3IF

End of enumeration elements list.

CAP0IC : CAP0IF clear bit
bits : 4 - 8 (5 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear CAP0IF

End of enumeration elements list.

MR9IC : MR9IF clear bit
bits : 5 - 10 (6 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear MR9IF

End of enumeration elements list.


PC

Offset:0x0C CT16Bn Prescale Counter Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC

PC : Prescaler Counter
bits : 0 - 7 (8 bit)
access : read-write



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