\n

UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RB

TH

DLL

LS

SP

ABCTRL

FD

CTRL

HDEN

DLM

IE

II

FIFOCTRL

LC


RB

Offset:0x00 UARTn Receiver Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RB RB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB

RB : The received byte in UART RX FIFO
bits : 0 - 7 (8 bit)
access : read-only


TH

Offset:0x00 UARTn Transmit Holding Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : RB
reset_Mask : 0x0

TH TH write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TH

TH : The byte to be transmitted in UART TX FIFO when transmitter is available
bits : 0 - 7 (8 bit)
access : write-only


DLL

Offset:0x00 UARTn Divisor Latch LSB Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : RB
reset_Mask : 0x0

DLL DLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL

DLL : DLL and DLM register determines the baud rate of UARTn
bits : 0 - 7 (8 bit)
access : read-write


LS

Offset:0x14 UARTn Line Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LS LS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR OE PE FE BI THRE TEMT RXFE

RDR : Receiver data ready flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : Not ready

UARTn_RB FIFO is empty

1 : Ready

UARTn_RB FIFO contains valid data

End of enumeration elements list.

OE : Overrun error flag
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0 : No overrun error

No overrun error

1 : Overrun error

Overrun error status is active

End of enumeration elements list.

PE : Parity error flag
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

0 : No parity error

No parity error

1 : Parity error

Parity error status is active

End of enumeration elements list.

FE : Framing error flag
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

0 : No framing error

No framing error

1 : Framing error

Framing error status is active

End of enumeration elements list.

BI : Break interrupt flag
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

0 : No break interrupt

No break interrupt

1 : Break interrupt

Break interrupt status is active

End of enumeration elements list.

THRE : THR empty flag
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : Not empty

THR contains valid data

1 : Empty

THR (TX FIFO) is empty

End of enumeration elements list.

TEMT : Transmitter empty flag
bits : 6 - 12 (7 bit)
access : read-only

Enumeration:

0 : Not empty

THR and/or TSR contains valid data

1 : Empty

THR and TSR are both empty

End of enumeration elements list.

RXFE : Receiver FIFO error flag
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : No RX FIFO error

UARTn_RB contains no UART RX errors

1 : RX FIFO error

UARTn_RB contains at least 1 UART RX error

End of enumeration elements list.


SP

Offset:0x1C UARTn Scratch Pad Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SP SP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD

PAD : Pad informaton
bits : 0 - 7 (8 bit)
access : read-write


ABCTRL

Offset:0x20 UARTn Auto-baud Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABCTRL ABCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START MODE AUTORESTART ABEOIFC ABTOIFC

START : Auto-baud run bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Stop

Auto-baud is not running

1 : Start

Auto-baud ids running

End of enumeration elements list.

MODE : Auto-baud mode selection
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Mode 0

Auto-baud mode 0

1 : Mode 1

Auto-baud mode 1

End of enumeration elements list.

AUTORESTART : Restart mode selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : No restart

No restart

1 : Restart

Auto restart in case of timeout

End of enumeration elements list.

ABEOIFC : Clear ABEOIF flag
bits : 8 - 16 (9 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear ABEOIF bit

End of enumeration elements list.

ABTOIFC : Clear ABTOIF flag
bits : 9 - 18 (10 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Clear

Clear ABTOIF bit

End of enumeration elements list.


FD

Offset:0x28 UARTn Fractional Divider Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FD FD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVADDVAL MULVAL OVER8

DIVADDVAL : Baud rate generation prescaler divisor value
bits : 0 - 3 (4 bit)
access : read-write

MULVAL : Baud rate generation prescaler multiplier value
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

0 : 0000

Baud rate prescaler multiplier value is 1

1 : 0001

Baud rate prescaler multiplier value is 2

2 : 0010

Baud rate prescaler multiplier value is 3

3 : 0011

Baud rate prescaler multiplier value is 4

4 : 0100

Baud rate prescaler multiplier value is 5

5 : 0101

Baud rate prescaler multiplier value is 6

6 : 0110

Baud rate prescaler multiplier value is 7

7 : 0111

Baud rate prescaler multiplier value is 8

8 : 1000

Baud rate prescaler multiplier value is 9

9 : 1001

Baud rate prescaler multiplier value is 10

10 : 1010

Baud rate prescaler multiplier value is 11

11 : 1011

Baud rate prescaler multiplier value is 12

12 : 1100

Baud rate prescaler multiplier value is 13

13 : 1101

Baud rate prescaler multiplier value is 14

14 : 1110

Baud rate prescaler multiplier value is 15

15 : 1111

Baud rate prescaler multiplier value is 16

End of enumeration elements list.

OVER8 : Oversampling value
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : 16

Oversampling by 16

1 : 8

Oversampling by 8

End of enumeration elements list.


CTRL

Offset:0x30 UARTn Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UARTEN MODE RXEN TXEN

UARTEN : USART enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable UART

1 : Enable

Enable UART

End of enumeration elements list.

MODE : UART mode
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

0 : 0

UART mode

End of enumeration elements list.

RXEN : RX enable
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Disable RX

1 : Enable

Enable RX

End of enumeration elements list.

TXEN : TX enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

Disable TX

1 : Enable

Enable TX

End of enumeration elements list.


HDEN

Offset:0x34 UARTn Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDEN HDEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDEN

HDEN : Half-duplex mode enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable half-duplex mode

1 : Enable

Enable half-duplex mode

End of enumeration elements list.


DLM

Offset:0x04 UARTn Divisor Latch MSB Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLM DLM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLM

DLM : DLL and DLM register determines the baud rate of USARTn
bits : 0 - 7 (8 bit)
access : read-write


IE

Offset:0x04 UARTn Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DLM
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDAIE THREIE RLSIE TEMTIE ABEOIE ABTOIE

RDAIE : RDA interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disable RDA interrupt

1 : Enable

Enable RDA interrupt

End of enumeration elements list.

THREIE : THRE interrupt enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disable THRE interrupt

1 : Enable

Enable THRE interrupt

End of enumeration elements list.

RLSIE : RLS interrupt enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Disable

Disable RLS interrupt

1 : Enable

Enable RLS interrupt

End of enumeration elements list.

TEMTIE : TEMT interrupt enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disable TEMT interrupt

1 : Enable

Enable TEMT interrupt

End of enumeration elements list.

ABEOIE : ABE0 interrupt enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : Disable

Disable ABEO interrupt

1 : Enable

Enable ABEO interrupt

End of enumeration elements list.

ABTOIE : ABT0 interrupt enable
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : Disable

Disable ABTO interrupt

1 : Enable

Enable ABTO interrupt

End of enumeration elements list.


II

Offset:0x08 UARTn Interrupt Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

II II read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSTATUS INTID FIFOEN ABEOIF ABTOIF

INTSTATUS : Interrupt status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : Pending

As least 1 interrupt is pending

1 : No interrupt

No interrupt

End of enumeration elements list.

INTID : Interrupt ID of RX FIFO
bits : 1 - 4 (4 bit)
access : read-only

Enumeration:

1 : 3a

THRE interrupt

2 : 2a

RDA (Receive Data Available)

3 : 1

RLS (Receive Line Status)

7 : 3b

TEMT interrupt

End of enumeration elements list.

FIFOEN : Equal to FIFOEN bits in USARTn_FIFOCTRL register
bits : 6 - 13 (8 bit)
access : read-only

ABEOIF : ABEO interrupt flag
bits : 8 - 16 (9 bit)
access : read-only

Enumeration:

0 : Not end

Auto-baud has not finished

1 : End

Auto-baud has finished and interrupt is enabled

End of enumeration elements list.

ABTOIF : ABTO interrupt flag
bits : 9 - 18 (10 bit)
access : read-only

Enumeration:

0 : Not Time-out

Auto-baud has not timed out

1 : Time-out

Auto-baud has timed out and interrupt is enabled

End of enumeration elements list.


FIFOCTRL

Offset:0x08 UARTn FIFO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FIFOCTRL FIFOCTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOEN RXTL

FIFOEN : FIFO enable
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : No effect

No effect

1 : Enable

Enable FIFO

End of enumeration elements list.

RXTL : RX trigger level
bits : 6 - 13 (8 bit)
access : write-only

Enumeration:

0 : Trigger level 0

1 character

End of enumeration elements list.


LC

Offset:0x0C UARTn Line Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LC LC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS SBS PE PS BC DLAB

WLS : Word length selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 5-bit

5-bit character

1 : 6-bit

6-bit character

2 : 7-bit

7-bit character

3 : 8-bit

8-bit character

End of enumeration elements list.

SBS : Stop bit selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : 1 stop bit

1 stop bit

1 : 2 stop bit

2 stop bit (1.5 stop bit if WLS=0)

End of enumeration elements list.

PE : Parity enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disable parity generation and checking

1 : Enable

Enable parity generation and checking

End of enumeration elements list.

PS : Parity selection
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

0 : 0

Odd parity

1 : 1

Even parity

2 : 2

Forced 1 sticky parity

3 : 3

Forced 0 sticky parity

End of enumeration elements list.

BC : Break control
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : Disable

Disable break transmission

1 : Enable

Enable break transmission

End of enumeration elements list.

DLAB : Divisor Latch access
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

Disable access to Divisor Latch

1 : Enable

Enable access to Divisor Latch

End of enumeration elements list.



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