Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Offset:0x00 I2Sn Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start Transmit/Receive
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Stop
Stop transmit/receive
1 : Start
Start transmit/receive
End of enumeration elements list.
MUTE : Mute enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disable mute
1 : Enable
Enable mute (I2SSDA output is 0)
End of enumeration elements list.
MONO : Mono/stereo selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : Stereo
Stereo mode
1 : Mono
Mono mode
End of enumeration elements list.
MS : Master/Slave selection bit
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Master
Act as Master using internally generated BCLK and WS signals.
1 : Slave
Act as Slave using externally BCLK and WS signals.
End of enumeration elements list.
FORMAT : I2S operation format
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : 0
Standard I2S format
1 : 01
Left-justified format
2 : 10
Right(MSB)-justified format
End of enumeration elements list.
TXEN : Transmit enable bit
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Disable TX
1 : Enable
Enable TX
End of enumeration elements list.
RXEN : Receiver enable bit
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Disable RX
1 : Enable
Enable RX
End of enumeration elements list.
CLRTXFIFO : Clear I2S TX FIFO
bits : 8 - 16 (9 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Reset TX FIFO
End of enumeration elements list.
CLRRXFIFO : Clear I2S RX FIFO
bits : 9 - 18 (10 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Reset RX FIFO
End of enumeration elements list.
DL : Data length
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : 8
Data length=8 bits
1 : 16
Data length=16 bits
2 : 24
Data length=24 bits
3 : 32
Data length=32 bits
End of enumeration elements list.
TXFIFOTH : TX FIFO threshold level
bits : 12 - 26 (15 bit)
access : read-write
Enumeration:
0 : 0
TX FIFO threshold level=0
1 : 1
TX FIFO threshold level=1
2 : 2
TX FIFO threshold level=2
3 : 3
TX FIFO threshold level=3
4 : 4
TX FIFO threshold level=4
5 : 5
TX FIFO threshold level=5
6 : 6
TX FIFO threshold level=6
7 : 7
TX FIFO threshold level=7
End of enumeration elements list.
RXFIFOTH : RX FIFO threshold level
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 0
RX FIFO threshold level=0
1 : 1
RX FIFO threshold level=1
2 : 2
RX FIFO threshold level=2
3 : 3
RX FIFO threshold level=3
4 : 4
RX FIFO threshold level=4
5 : 5
RX FIFO threshold level=5
6 : 6
RX FIFO threshold level=6
7 : 7
RX FIFO threshold level=7
End of enumeration elements list.
CHLENGTH : Bit number of single channel
bits : 20 - 44 (25 bit)
access : read-write
Enumeration:
7 : 7
8 bits
8 : 8
9 bits
9 : 9
10 bits
10 : 10
11 bits
11 : 11
12 bits
12 : 12
13 bits
13 : 13
14 bits
14 : 14
15 bits
15 : 15
16 bits
16 : 16
17 bits
17 : 17
18 bits
18 : 18
19 bits
19 : 19
20 bits
20 : 20
21 bits
21 : 21
22 bits
22 : 22
23 bits
23 : 23
24 bits
24 : 24
25 bits
25 : 25
26 bits
26 : 26
27 bits
27 : 27
28 bits
28 : 28
29 bits
29 : 29
30 bits
30 : 30
31 bits
31 : 31
32 bits (Max)
End of enumeration elements list.
I2SEN : I2S enable
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : Disable
Disable I2S
1 : Enable
Enable I2S
End of enumeration elements list.
Offset:0x10 I2Sn Raw Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFIFOOVIF : TX FIFO overflow interrupt flag
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : 0
No TX FIFO overflow
1 : 1
TX FIFO overflow
End of enumeration elements list.
RXFIFOUDIF : RX FIFO underflow interrupt flag
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : 0
No RX FIFO underflow
1 : 1
RX FIFO underflow
End of enumeration elements list.
TXFIFOTHIF : TX FIFO threshold interrupt flag
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : 0
No TX FIFO threshold interrupt
1 : 1
TX FIFO threshold triggered
End of enumeration elements list.
RXFIFOTHIF : RX FIFO threshold interrupt flag
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : 0
No RX FIFO threshold interrupt
1 : 1
RX FIFO threshold triggered
End of enumeration elements list.
Offset:0x14 I2Sn Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXFIFOOVIC : TX FIFO overflow interrupt clear
bits : 4 - 8 (5 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear TXFIFOOVIF bit
End of enumeration elements list.
RXFIFOUDIC : RX FIFO underflow interrupt clear
bits : 5 - 10 (6 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear RXFIFOUDIF bit
End of enumeration elements list.
TXFIFOTHIC : TX FIFO threshold interrupt clear
bits : 6 - 12 (7 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear TXFIFOTHIF bit
End of enumeration elements list.
RXFIFOTHIC : RX FIFO threshold interrupt clear
bits : 7 - 14 (8 bit)
access : write-only
Enumeration:
0 : No effect
No effect
1 : Clear
Clear RXFIFOTHIF bit
End of enumeration elements list.
Offset:0x18 I2Sn RX FIFO Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Offset:0x1C I2Sn TX FIFO Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Offset:0x04 I2Sn Clock Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKDIV : MCLK divider
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : 0
MCLK=MCLK source
1 : 1
MCLK=MCLK source/2
2 : 2
MCLK=MCLK source/4
3 : 3
MCLK=MCLK source/6
4 : 4
MCLK=MCLK source/8
5 : 5
MCLK=MCLK source/10
6 : 6
MCLK=MCLK source/12
7 : 7
MCLK=MCLK source/14
End of enumeration elements list.
MCLKOEN : MLCK output enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disable MCLK output
1 : Enable
Enable MCLK output
End of enumeration elements list.
MCLKSEL : MLCK source selection
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : I2S_PCLK
MCLK source of master is from I2S_PCLK
1 : GPIO
MCLK source of master is from GPIO
End of enumeration elements list.
BCLKDIV : BCLK divider
bits : 8 - 23 (16 bit)
access : read-write
CLKSEL : I2S clock source
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : HCLK
HCLK is I2S clock source
1 : EHS XTAL
EHS Xtal is I2S clock source
End of enumeration elements list.
Offset:0x08 I2Sn Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2SINT : I2S interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : No
No I2S interrupt
1 : Occurs
I2S interrupt occurs
End of enumeration elements list.
RIGHTCH : Current channel status
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : Left
Current channel is left channel
1 : Right
Current channel is right channel
End of enumeration elements list.
TXFIFOTHF : TX FIFO threshold flag
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
0 : 0
TXFIFOLV is larger equal than TXFIFOTH
1 : 1
TXFIFOLV is less than TXFIFOTH
End of enumeration elements list.
RXFIFOTHF : RX FIFO threshold flag
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : 0
RXFIFOLV is less equal than RXFIFOTH
1 : 1
RXFIFOLV is larger than RXFIFOTH
End of enumeration elements list.
TXFIFOFULL : TX FIFO full flag
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
0 : Not full
TX FIFO is not full
1 : Full
TX FIFO is full
End of enumeration elements list.
RXFIFOFULL : RX FIFO full flag
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
0 : 0
RX FIFO is not full
1 : 1
RX FIFO is full
End of enumeration elements list.
TXFIFOEMPTY : TX FIFO empty flag
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
0 : 0
TX FIFO is not empty
1 : 1
TX FIFO is empty
End of enumeration elements list.
RXFIFOEMPTY : RX FIFO empty flag
bits : 11 - 22 (12 bit)
access : read-only
Enumeration:
0 : 0
RX FIFO is not empty
1 : 1
RX FIFO is empty
End of enumeration elements list.
TXFIFOLV : TX FIFO used level
bits : 12 - 27 (16 bit)
access : read-only
Enumeration:
0 : 0
0/8 TX FIFO is used (Empty)
1 : 1
1/8 TX FIFO is used
2 : 2
2/8 TX FIFO is used
3 : 3
3/8 TX FIFO is used
4 : 4
4/8 TX FIFO is used
5 : 5
5/8 TX FIFO is used
6 : 6
6/8 TX FIFO is used
7 : 7
7/8 TX FIFO is used
8 : 8
8/8 TX FIFO is used (Full)
End of enumeration elements list.
RXFIFOLV : RX FIFO used level
bits : 17 - 37 (21 bit)
access : read-only
Enumeration:
0 : 0
0/8 RX FIFO is used (Empty)
1 : 1
1/8 RX FIFO is used
2 : 2
2/8 RX FIFO is used
3 : 3
3/8 RX FIFO is used
4 : 4
4/8 RX FIFO is used
5 : 5
5/8 RX FIFO is used
6 : 6
6/8 RX FIFO is used
7 : 7
7/8 RX FIFO is used
8 : 8
8/8 RX FIFO is used (Full)
End of enumeration elements list.
Offset:0x0C I2Sn Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFIFOOVFIEN : TX FIFO overflow interrupt enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Disable TX FIFO overflow interrupt
1 : Enable
Enable TX FIFO overflow interrupt
End of enumeration elements list.
RXFIFOUDFIEN : RX FIFO underflow interrupt enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Disable RX FIFO underflow interrupt
1 : Enable
Enable RX FIFO underflow interrupt
End of enumeration elements list.
TXFIFOTHIEN : TX FIFO threshold interrupt enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : Disable
Disable TX FIFO threshold interrupt
1 : Enable
Enable TX FIFO threshold interrupt
End of enumeration elements list.
RXFIFOTHIEN : RX FIFO threshold interrupt enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Disable RX FIFO threshold interrupt
1 : Enable
Enable RX FIFO threshold interrupt
End of enumeration elements list.
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