\n

CRC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

DATA


CTRL

Offset:0x0 CRC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC RESET URCRCEN BUSY

CRC : CRC Polynomial
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : CRC-16-CCITT

CRC-16-CCITT Polynomial

1 : CRC-16

CRC-16 Polynomial

2 : CRC-32

CRC-32 Polynomial

End of enumeration elements list.

RESET : CRC Reset bit
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : No

No effect

1 : Reset

Reset CRC circuit

End of enumeration elements list.

URCRCEN : CRC calculation for the User ROM enable bit
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Stop/Finish

Stop/Finish CRC calculation

1 : Enable

Start CRC calculation for the User ROM

End of enumeration elements list.

BUSY : CRC calculation busy flag
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

0 : Idle/Finish

CRC calculation idle/finished

1 : Busy

CRC calculation is in process

End of enumeration elements list.


DATA

Offset:0x4 CRC Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRC Data
bits : 0 - 31 (32 bit)
access : read-write



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