DR

FR

LCRH_RX

IBRD

FBRD

LCRH_TX

CR

IFLS

IMSC

RIS

RSR

ECR

MIS

ICR

DMACR

XFCR

XON1

XON2

XOFF1

XOFF2

TIMEOUT

DATA : UART data register:

• Receive: read data character.
• Transmit: write data character.

bits : 0 - 7 (8 bit)
access : read-write

FE : Frame error. This bit is set to 1 if the received character did not have a valid stop bit. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 8 - 8 (1 bit)
access : read-only

PE : Parity error. This bit is set to 1 if the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCRH_RX register. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 9 - 9 (1 bit)
access : read-only

BE : Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to HIGH (marking state), and the next valid start bit is received
bits : 10 - 10 (1 bit)
access : read-only

OE : Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0b once there is an empty space in the FIFO and a new character can be written to it. The FIFO content remains valid since no further data is written when the FIFO is full, only the content of the shift register is overwritten.
bits : 11 - 11 (1 bit)
access : read-only

CTS : Clear to send.
bits : 0 - 0 (1 bit)

BUSY : UART Busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. However, if the transmit section of the UART is disabled in the middle of a transmission, the BUSY bit gets cleared. This bit is set again once the transmit section is re-enabled to complete the remaining transmission.This bit is set as soon as the transmit FIFO becomes nonempty (regardless of whether the UART is enabled or not).
bits : 3 - 3 (1 bit)

RXFE : Receive FIFO empty. If the FIFO is disabled (bit FEN = 0b), this bit is set when the receive holding register is empty. If the FIFO is enabled (FEN = 1b), the RXFE bit is set when the receive FIFO is empty.
bits : 4 - 4 (1 bit)

TXFF : Transmit FIFO full. If the FIFO is disabled (bit FEN = 0b), this bit is set when the transmit holding register is full. If the FIFO is enabled (FEN = 1b), the TXFF bit is set when the transmit FIFO is full.
bits : 5 - 5 (1 bit)

RXFF : Receive FIFO full. If the FIFO is disabled (bit FEN = 0b), this bit is set when the receive holding register is full. If the FIFO is enabled (FEN = 1b), the RXFF bit is set when the receive FIFO is full.
bits : 6 - 6 (1 bit)

TXFE : Transmit FIFO empty. If the FIFO is disabled (bit FEN = 0b), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN = 1b), the TXFE bit is set when the transmit FIFO is empty.
bits : 7 - 7 (1 bit)

DCTS : Delta Clear To Send. This bit is set CTS changes since the last read of the FR register.
bits : 9 - 9 (1 bit)

RTXDIS : Remote Transmitter Disabled (software flow control). This bit indicates an Xoff character was sent to the remote transmitter to stop it after the received FIFO has passed over its trigger limit. This bit is cleared when a Xon character is sent to the remote transmitter.
bits : 13 - 13 (1 bit)

PEN_RX : RX parity enable:

• 0: Parity disabled.
• 1: Parity enabled.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

EPS_RX : RX even parity selection, when the parity is enabled.

• 0: Odd parity generation and checking is performed during reception, which check for an odd number of 1s in data and parity bits.
• 1: Even parity generation and checking is performed during reception, which check for an even number of 1s in data and parity bits.

bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

STP2_RX : RX two stop bits select. This bit enables the check for two stop bits being received:

• 0: 1 stop bit received.
• 1: 2 stop bits received.

bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

FEN_RX : RX enable FIFOs. This bit enables/disables the receive RX FIFO buffer:

• 0: RX FIFO is disabled (character mode).
• 1: RX FIFO is enabled.

bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

WLEN_RX : RX Word length. This bit field indicates the number of data bits received in a frame as follows:

• 00b: 5 bits.
• 01b: 6 bits.
• 10b: 7 bits.
• 11b: 8 bits.

bits : 5 - 6 (2 bit)

Enumeration:

End of enumeration elements list.

SPS_RX : RX stick parity select:

• 0: stick parity is disabled.
• 1: when PEN_RX = 1b (parity enabled) and EPS_RX = 1b (even parity), the parity is checked as a 0. When PEN_RX = 1b and EPS_RX = 0b (odd parity), the parity bit is checked as a 1.

bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

DIVINT : Baud rate integer. The baud rate divisor is calculated as follows:

When OVSFACT = 0b in the CR register: Baud rate divisor = (Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor = (Frequency (UARTCLK)/(8*Baud rate))

where Frequency (UARTCLK) is the UART reference clock frequency. The baud rate divisor comprises the integer value (DIVINT) and the fractional value (DIVFRAC). The contents of the IBRD and FBRD registers are not updated until transmission or reception of the current character has completed.
bits : 0 - 15 (16 bit)

DIVFRAC : Baud rate fraction. Baud rate integer. The baud rate divisor is calculated as follows:

When OVSFACT = 0b in the CR register: Baud rate divisor = (Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor = (Frequency (UARTCLK)/(8*Baud rate))

where Frequency (UARTCLK) is the UART reference clock frequency. The baud rate divisor comprises the integer value (DIVINT) and the fractional value (DIVFRAC). The contents of the IBRD and FBRD registers are not updated until transmission or reception of the current character has completed.
bits : 0 - 5 (6 bit)

BRK : Send break. This bit allows a continuous low-level to be forced on TX output, after completion of the current character. This bit must be asserted for at least one complete frame transmission time in order to generate a break condition. The transmit FIFO contents remain unaffected during a break condition.

• 0: Normal transmission.
• 1: Break condition transmission.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

PEN_TX : TX parity enable:

• 0: Parity disabled.
• 1: Parity Enable.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

EPS_TX : TX even parity select. This bit selects the parity generation, when the parity is enabled (PEN_TX =1b). This bit has no effect when parity is disabled (PEN_TX = 0b).

• 0: Odd parity generation and checking is performed during transmission, which check for an odd number of 1s in data and parity bits.
• 1: Even parity generation and checking is performed during transmission, which check for an even number of 1s in data and parity bits.

bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

STP2_TX : TX two stop bits select. This bit enables the check for two stop bits being received:

• 0: 1 stop bit received.
• 1: 2 stop bits received.

bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

FEN_TX : TX Enable FIFO. This bit enables/disables the transmit TX FIFO buffer:

• 0: TX FIFO is disabled (character mode), i.e. the TX FIFO becomes a 1-byte deep holding register.
• 1: TX FIFO is enabled.

bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

WLEN_TX : TX word length. This bit field indicates the number of data bits transmitted in a frame as follows:

• 00b: 5 bits.
• 01b: 6 bits.
• 10b: 7 bits.
• 11b: 8 bits.

bits : 5 - 6 (2 bit)

Enumeration:

End of enumeration elements list.

SPS_TX : TX Stick parity check:

• 0: stick parity disable.
• 1: when PEN_TX = 1b (parity enabled) and EPS_TX = 1b (even parity), the parity is transmitted as a 0. When PEN_TX = 1b and EPS_TX = 0b (odd parity), the parity bit is transmitted as a 1.

bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

UARTEN : UART enable. This bit enables the UART.

• 0: UART is disabled.
• 1: UART is enabled. Data transmission and reception can occur. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

OVSFACT : UART oversampling factor.This bit enables the UART oversampling factor. If UARTCLK is 16 MHz thus max. baud-rate is 1 Mbaud when OVSFACT = 0b, and 2 Mbaud when OVSFACT = 1b.

• 0: UART it is 16 UARTCLK clock cycles.
• 1: UART it is 8 UARTCLK clock cycles.

bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

TXE : Transmit enable.

• 0b: UART TX disabled.
• 1b: UART TX enabled.

bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

RXE : Receive enable.

• 0b: UART RX disabled.
• 1b: UART RX enabled.

bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

RTS : Request to send.

• 0: RTS is high.
• 1: RTS is low.

bits : 11 - 11 (1 bit)

Enumeration:

End of enumeration elements list.

RTSEN : RTS hardware flow control enable.

• 0b: RTS disabled.
• 1b: RTS enabled. Data is only requested when there is space in the receive FIFO for it to be received.

bits : 14 - 14 (1 bit)

Enumeration:

End of enumeration elements list.

CTSEN : CTS hardware flow control enable.

• 0b: CTS disabled.
• 1b: CTS enabled. Data is only transmitted when the CTS is asserted.

bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

STA_B_DURATION : START bit duration Receiver state. These bits can be used to configure the START bit duration (in clock cycles) to get the bit sampled in the middle of the UART receiver. These bits can be used only when using high baud rates (IBRD = 1, FBRD >= 0 and OVSFACT = 1). Below the formula to calculate the START bit duration receiver state:

STA_B_DURATION = Integer(Fuartclk/(2* BAUD RATE)) - 1

Example: when UARTCLK = 16 MHz and BAUD RATE = 2.0 Mbps then STA_B_DURATION = 4 - 1 = 3. STA_B_DURATION field should be configured with 4'b0011.
bits : 16 - 19 (4 bit)

TXIFLSEL : Transmit interrupt FIFO level select. This bit field selects the trigger points for TX FIFO interrupt:

• 000b: Interrupt when FIFO >= 1/64 empty.
• 001b: Interrupt when FIFO >= 1/32 empty.
• 010b: Interrupt when FIFO >= 1/16 empty.
• 011b: Interrupt when FIFO >= 1/8 empty.
• 100b: Interrupt when FIFO >= 1/4 empty.
• 101b: Interrupt when FIFO >= 1/2 empty.
• 110b: Interrupt when FIFO >= 3/4 empty.

bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

RXIFLSEL : Receive interrupt FIFO level select. This bit field selects the trigger points for RX FIFO interrupt:

• 000b: Interrupt when FIFO >= 1/64 full.
• 001b: Interrupt when FIFO >= 1/32 full.
• 010b: Interrupt when FIFO >= 1/16 full.
• 011b: Interrupt when FIFO >= 1/8 full.
• 100b: Interrupt when FIFO >= 1/4 full.
• 101b: Interrupt when FIFO >= 1/2 full.
• 110b: Interrupt when FIFO >= 3/4 full.

bits : 3 - 5 (3 bit)

Enumeration:

End of enumeration elements list.

CTSMIM : Clear to send modem interrupt mask. On a read, the current mask for the CTSMIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

RXIM : Receive interrupt mask. On a read, the current mask for the RXIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 4 - 3 ( bit)

TXIM : Transmit interrupt mask. On a read, the current mask for the TXIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 5 - 4 ( bit)

RTIM : Receive timeout interrupt mask. On a read, the current mask for the RTIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 6 - 5 ( bit)

FEIM : Framing error interrupt mask. On a read, the current mask for the FEIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 7 - 6 ( bit)

PEIM : Parity error interrupt mask. On a read, the current mask for the PEIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 8 - 7 ( bit)

BEIM : Break error interrupt mask. On a read, the current mask for the BEIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 9 - 8 ( bit)

OEIM : Overrun error interrupt mask. On a read, the current mask for the OEIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 10 - 9 ( bit)

XOFFIM : XOFF interrupt mask. On a read, the current mask for the XOFFIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 11 - 10 ( bit)

TXFEIM : TX FIFO empty interrupt mask. On a read, the current mask for the TXFEIM interrupt is returned.

• 0: Clears the mask (interrupt is disabled).
• 1: Sets the mask (interrupt is enabled).

bits : 12 - 11 ( bit)

CTSMIS : Clear to send interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

RXIS : Receive interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 4 - 4 (1 bit)

TXIM : Transmit interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 5 - 5 (1 bit)

RTIS : Receive timeout interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 6 - 6 (1 bit)

FEIS : Framing error interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 7 - 7 (1 bit)

PEIS : Parity error interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 8 - 8 (1 bit)

BEIS : Break error interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 9 - 9 (1 bit)

OEIS : Overrun error interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 10 - 10 (1 bit)

XOFFIS : XOFF interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 11 - 11 (1 bit)

TXFEIS : TX FIFO empty interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 12 - 12 (1 bit)

FE : Frame error. This bit is set to 1 if the received character did not have a valid stop bit (a valid stop bit is 1).This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 0 - 0 (1 bit)
access : read-only

PE : Parity error. This bit is set to 1 if the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCRH_RX register.This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
bits : 1 - 1 (1 bit)
access : read-only

BE : Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits). This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to HIGH (marking state), and the next valid start bit is received.
bits : 2 - 2 (1 bit)
access : read-only

OE : Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 by a write to ECR (data value is not important). The FIFO contents remain valid since no further data is written when the FIFO is full, only the content of the shift register are overwritten. The CPU or DMA must now read the data in order to empty the FIFO.
bits : 3 - 3 (1 bit)
access : read-only

CTSMMIS : Clear to send masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

RXMIS : Receive masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 4 - 4 (1 bit)

TXMIS : Transmit masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 5 - 5 (1 bit)

RTMIS : Receive timeout masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 6 - 6 (1 bit)

FEMIS : Framing error masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 7 - 7 (1 bit)

PEMIS : Parity error masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 8 - 8 (1 bit)

BEMIS : Break error masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 9 - 9 (1 bit)

OEMIS : Overrun error masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 10 - 10 (1 bit)

XOFFMIS : XOFF interrupt masked status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 11 - 11 (1 bit)

TXFEMIS : TX FIFO empty masked interrupt status.

• 0: The interrupt is not pending.
• 1: The interrupt is pending.

bits : 12 - 12 (1 bit)

CTSMIC : Clear to send modem interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 1 - 1 (1 bit)

RXIC : Receive interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 4 - 4 (1 bit)

TXIC : Transmit interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 5 - 5 (1 bit)

RTIC : Receive timeout interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 6 - 6 (1 bit)

FEIC : Framing error interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 7 - 7 (1 bit)

PEIC : Parity error interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 8 - 8 (1 bit)

BEIC : Break error interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 9 - 9 (1 bit)

OEIC : Overrun error interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 10 - 10 (1 bit)

XOFFIC : XOFF interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 11 - 11 (1 bit)

TXFEIC : TX FIFO empty interrupt clear.

• 0: No effect.
• 1: Clears the interrupt.

bits : 12 - 12 (1 bit)

RXDMAE : Receive DMA enable bit.

• 0: DMA mode is disabled for reception.
• 1: DMA mode is enabled for reception.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

TXDMAE : Transmit DMA enable bit.

• 0: DMA mode is disabled for transmit.
• 1: DMA mode is enabled for transmit.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

DMAONERR : DMA on error.

• 0: UART error interrupt status has no impact in receive DMA mode.
• 1: DMA receive requests are disabled when the UART error interrupt is asserted.

bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

SFEN : Software flow control enable.

• 0: Software flow control disable.
• 1: software flow control enable.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

SFRMOD : Software receive flow control mode:

• 00b: Receive flow control is disabled.
• 01b: Xon1, Xoff1 characters are used in receiving software flow control.
• 10b: Xon2, Xoff2 characters are used in receiving software flow control.
• 11b: Xon1 and Xon2, Xoff1 and Xoff2 characters are used in receiving software flow control.

bits : 1 - 2 (2 bit)

Enumeration:

End of enumeration elements list.

SFTMOD : Software transmit flow control mode:

• 00b: Transmit flow control is disabled.
• 01b: Xon1, Xoff1 characters are used in transmitting software flow control.
• 10b: Xon2, Xoff2 characters are used in transmitting software flow control.
• 11b: Xon1 and Xon2, Xoff1 and Xoff2 characters are used in transmitting software flow control.

bits : 3 - 4 (2 bit)

Enumeration:

End of enumeration elements list.

XONANY : Xon-any bit:

• 0: Incoming character must match Xon programmed value(s) to be a valid Xon.
• 1: Any incoming character is considered as a valid Xon.

bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

SPECHAR : Special character detection bit.

• 0: Special character detection disabled.
• 1: Special character detection enabled.

bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

XON1 : Value of Xon1 character used in the software flow control
bits : 0 - 7 (8 bit)

XON2 : Value of Xon2 character used in the software flow control
bits : 0 - 7 (8 bit)

XOFF1 : Value of Xoff1 character used in the software flow control
bits : 0 - 7 (8 bit)

XOFF2 : Value of Xoff2 character used in the software flow control
bits : 0 - 7 (8 bit)

PERIOD : Timeout period configuration. This bit field contains the timeout period for the UART timeout interrupt assertion. The receive timeout interrupt is asserted when the receive FIFO is not empty and no further data is received over a programmed timeout period. The duration before the timeout interrupt will assert is calculated by the following formula:

Timeout_Duration = (TIMEOUT_PERIOD) / (OVSP * Baud_Rate)

or

Timeout_Duration = (TIMEOUT_PERIOD) * Baud_Divisor * Tuartclk

bits : 0 - 21 (22 bit)