CR0

CPSR

IMSC

RIS

MIS

ICR

DMACR

RXFRM

CHN

WDTXF

CR1

DR

ITCR

TDR

SR

DSS : Data size select. (DSS+1) defines the number of bits:

• 0x00: Reserved.
• 0x01: Reserved.
• 0x02: Reserved.
• 0x03: 4-bit data.
• 0x04: 5-bit data.
• ...
• 0x1F: 32-bit data.

bits : 0 - 4 (5 bit)

Enumeration:

End of enumeration elements list.

SPO : Clock polarity.

• 0: Steady state of clock polarity is low.
• 1: Steady state of clock polarity is high.

bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

SPH : Clock phase.

• 0: Steady state of clock phase is low.
• 1: Steady state of clock phase is high.

bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

SCR : Serial Clock Rate.

The SRC value is used to generate the transmit and receive bit rate of the SPI. The bit rate is: f_SPICLK / (CPSDVR * (1 + SCR)), where CPSDVR is an even value from 2 to 254 and SCR is a value from 0 to 255.

bits : 8 - 15 (8 bit)

SPIM : SPI transmission mode.

• 00b: Full duplex mode.
• 01b: Transmit mode.
• 10b: Receive mode.
• 11b: Combined mode.

bits : 23 - 24 (2 bit)

Enumeration:

End of enumeration elements list.

INVCLK : Activate inversion (in master mode only).

• 0: Master samples the received data respecting the Motorola SPI protocol.
• 1: The sampling of the received data by master is delayed by half an SPI clock cycle..

bits : 25 - 25 (1 bit)

CS1 : Chip Selection for slave one

• 0: the slave 1 is selected.
• 1: the slave 1 is not selected.

bits : 26 - 26 (1 bit)

Enumeration:

End of enumeration elements list.

CPSDVSR : Clock prescale divisor.It must be an even number from 2 to 254. The value is used to generate the transmit and receive bit rate of the SPI. The bit rate is:

FSSPCLK / [CPSDVR x (1+SCR)]

where SCR is a value from 0 to 255, programmed through the SSP_CR0 register.
bits : 0 - 7 (8 bit)

RORIM : Receive overrun interrupt mask:

• 0: RX FIFO written to while full condition interrupt is masked (irq disabled).
• 1: RX FIFO written to while full condition interrupt is not masked (irq enabled).

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RTIM : Receive timeout interrupt mask:

• 0: RX FIFO not empty or no read prior to the timeout period interrupt is masked (irq disabled).
• 1: RX FIFO not empty or no read prior to the timeout period interrupt is not masked (irq enabled).

bits : 1 - 1 (1 bit)

RXIM : Receive FIFO interrupt mask:

• 0: Receive interrupt is masked (irq disabled).
• 1: Receive interrupt is not masked (irq enabled).

bits : 2 - 2 (1 bit)

TXIM : Transmit FIFO interrupt mask:

• 0: Transmit interrupt is masked (irq disabled).
• 1: Transmit interrupt is not masked (irq enabled).

bits : 3 - 3 (1 bit)

TURIM : Transmit underrun interrupt mask:

• 0: Transmit underrun interrupt is masked (irq disabled).
• 1: Transmit underrun interrupt is not masked (irq enabled).

bits : 4 - 4 (1 bit)

TEIM : Transmit FIFO empty interrupt mask:

• 0: TX FIFO empty interrupt is masked (irq disabled).
• 1: TX FIFO empty interrupt is not masked (irq enabled).

bits : 5 - 5 (1 bit)

RORRIS : Receive overrun raw interrupt status
bits : 0 - 0 (1 bit)

RTRIS : Receive time out raw interrupt status
bits : 1 - 1 (1 bit)

RXRIS : Receive raw interrupt status
bits : 2 - 2 (1 bit)

TXRIS : Transmit raw interrupt status
bits : 3 - 3 (1 bit)

TURRIS : Transmit underrun raw interrupt Status
bits : 4 - 4 (1 bit)

TERIS : Transmit FIFO Empty Raw Interrupt Status
bits : 5 - 5 (1 bit)

RORMIS : Receive Overrun Masked Interrupt Status: gives the interrupt status after masking of the receive overrun interrupt.
bits : 0 - 0 (1 bit)

RTMIS : Receive Time Out Masked Interrupt Status: gives the interrupt status after masking of receive timeout interrupt.
bits : 1 - 1 (1 bit)

RXMIS : Receive Masked Interrupt Status: gives the interrupt status after masking of the receive interrupt.
bits : 2 - 2 (1 bit)

TXMIS : Transmit Masked Interrupt Status: gives the interrupt status after masking of the transmit interrupt.
bits : 3 - 3 (1 bit)

TURMIS : Transmit Underrun Masked Interrupt Status: gives the interrupt status after masking of the transmit underrun interrupt.
bits : 4 - 4 (1 bit)

TEMIS : Transmit FIFO Empty Masked Interrupt Status: gives the interrupt status after masking of the transmit FIFO empty interrupt.
bits : 5 - 5 (1 bit)

RORIC : Receive Overrun Clear Interrupt: writing 1 clears the receive overrun interrupt.
bits : 0 - 0 (1 bit)

RTIC : Receive Time Out Clear Interrupt: writing 1 clears the receive timeout interrupt.
bits : 1 - 1 (1 bit)

TURIC : Transmit Underrun Clear Interrupt: writing 1 clears the transmit overrun interrupt.
bits : 2 - 2 (1 bit)

RXDMASE : Single receive DMA request.

• 0: Single transfer DMA in receive disable.
• 1: Single transfer DMA in receive enable.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

TXDMASE : Signle transmit DMA request.

• 0: Single transfer DMA in transmit disable.
• 1: Single transfer DMA in transmit enable.

bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

SSE : SPI enable.

• 0: SPI disable.
• 1: SPI enable.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

MS : Master or slave mode select.

• 0: Master mode.
• 1: Slave mode.

bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

SOD : Slave mode output disable (slave mode only).

• 0: SPI can drive the MISO signal in slave mode.
• 1: SPI must not drive the MISO signal in slave mode.

In multiple slave system, it is possible for a SPI master to broadcast a message to all slaves in the system while ensuring only one slave drives data onto the serial output line MISO.
bits : 3 - 3 (1 bit)

RENDN : Receive endian format.

• 00b: The element is received MSByte-first and MSbit-first.
• 01b: The element is received LSByte-first and MSbit-first.
• 10b: The element is received MSByte-first and LSbit-first.
• 11b: The element is received LSByte-first and LSbit-first.

The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits.
bits : 4 - 5 (2 bit)

Enumeration:

End of enumeration elements list.

RXIFLSEL : Receive interrupt FIFO level select. This bit field selects the trigger points to receive FIFO interrupt:

• 000b: RX FIFO contains 1 element or more.
• 001b: RX FIFO contains 4 elements or more.
• 010b: RX FIFO contains 8 elements or more.
• Others: Reserved.

bits : 7 - 9 (3 bit)

Enumeration:

End of enumeration elements list.

TXIFLSEL : Transmit interrupt FIFO level select. This bit field selects the trigger points to transmit FIFO interrupt:

• 000b: TX FIFO contains 1 element or more.
• 001b: TX FIFO contains 4 elements or more.
• 010b: TX FIFO contains 8 elements or more.
• Others: Reserved.

bits : 10 - 12 (3 bit)

Enumeration:

End of enumeration elements list.

FLOWCTRLEN : Flow Control Enable.

• 0: Flow control is disabled.
• 1: Flow control is enabled.

bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

MSPIWAIT : SPI Wait mode. This value is used to insert a wait state between frames.
bits : 14 - 17 (4 bit)

TENDN : Transmit endian format.

• 00b: The element is transmitted MSByte-first and MSbit-first.
• 01b: The element is transmitted LSByte-first and MSbit-first.
• 10b: The element is transmitted MSByte-first and LSbit-first.
• 11b: The element is transmitted LSByte-first and LSbit-first.

The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits.
bits : 18 - 19 (2 bit)

DATAINDEL : Data input delay.

• 0: No delay is inserted in data input.
• 1: A delay of 2 clock cycles is inserted in the data input path.

bits : 21 - 21 (1 bit)

DATA : Transmit/Receive data:

• Read: RX FIFO is read.
• Write: TX FIFO is written.

Data must be right-justified when a data size of less than 32-bit is programmed. Unused bits are ignored by the transmit logic. The receive logic automatically right-justifies data.
bits : 0 - 31 (32 bit)

SWAPFIFO : FIFO control mode:

• 0: FIFO normal mode. Write in TDR register puts data in TX FIFO and read from TDR register read data from RX FIFO.
• 1: FIFO swapped mode. Write in TDR register puts data in RX FIFO and read from TDR register read data from TX FIFO.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

TFE : Transmit FIFO empty:

• 0: TX FIFO is not empty.
• 1: TX FIFO is empty.

bits : 0 - 0 (1 bit)

TNF : Transmit FIFO not full:

• 0: TX FIFO is full.
• 1: TX FIFO is not full.

bits : 1 - 1 (1 bit)

RNE : Receive FIFO not empty:

• 0: RX FIFO is empty.
• 1: RX FIFO is not empty.

bits : 2 - 2 (1 bit)

RFF : Receive FIFO full:

• 0: RX FIFO is not full.
• 1: RX FIFO is full.

bits : 3 - 3 (1 bit)

BSY : SPI busy flag:

• 0: SPI is idle.
• 1: SPI is currently transmitting and/or receiving a frame or the TX FIFO is not empty.

bits : 4 - 4 (1 bit)