LR

RIS

MIS

VAL

CR

ICR

LOCK

LOAD : Watchdog load value. Value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value.
bits : 0 - 31 (32 bit)

RIS : Watchdog raw interrupt status bit. Reflects the status of the interrupt status from the watchdog:

• 0: watchdog interrupt is not active.
• 1: watchdog interrupt is active.

Read-only bit. A write has no effect.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

MIS : Watchdog masked interrupt status bit. Masked value of watchdog interrupt status:

• 0: watchdog interrupt is not active.
• 1: watchdog interrupt is active.

Read-only bit. A write has no effect.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

WDTVAL : Watchdog load value. When read, returns the current value of the decrementing watchdog counter. A write has no effect.
bits : 0 - 31 (32 bit)

INTEN : Watchdog interrupt enable. Enable the interrupt event:

• 0: watchdog interrupt is disabled.
• 1: watchdog interrupt is enabled.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RESEN : Watchdog reset enable. Enable the watchdog reset output:

• 0: watchdog reset is disabled.
• 1: watchdog reset is enabled.

bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

WDTICLR : Watchdog interrupt enable:

• Writing any value will clear the watchdog interrupt and reloads the counter from the LR register.
• A read returns zero.

bits : 0 - 31 (32 bit)

LOCKVAL : Watchdog lock value. When read, returns the lock status:

• 0: Write access to all watchdog other registers is enabled.
• 1: Write access to all watchdog other registers is disabled.

When written, allows enabling or disabling write access to all other watchdog registers:

• Writing 0x1ACCE551: Write access to all other registers is enabled.
• Writing any other value: Write access to all other registers is disabled.

bits : 0 - 31 (32 bit)