DATA_CONV

OFFSET

CTRL

SR_REG

THRESHOLD_HI

THRESHOLD_LO

CONF

IRQSTAT

IRQMASK

ON : Starts ADC analog subsystem. This bit must be set before starting a conversion.

• 0: ADC is OFF.
• 1: ADC is ON.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

CALEN : Enables the calibration phase when set to 1. This bit is cleared and the calibration is disabled by setting the RSTADCCALEN bit.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SWSTART : Starts the ADC conversion phase when set.
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

RESET : Reset all the ADC APB registers when set.
bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

STOP : Permits to stop the continuous conversion.

• 0: continuous conversion is enabled but SWSTART and ADCON bits must be set.
• 1: stop the continuous conversion and switch off the ADC.

bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

ENAB_COMP : Enables the window comparator when set to 1. WDOG flag is ADC_SR register is set if the converted value is between ADCTHRESHOLD_HI and ADCTHRESHOLD_LO value.
bits : 5 - 5 (1 bit)

RSTCALEN : Disable the calibration phase when set to 1. This bit has to be set to disable the calibration each time calibration is enabled.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

AUTO_OFFSET : Enables the update of ADC_OFFSET register.

• 0: ADC_OFFSET register is not updated.
• 1: ADC_OFFSET register is updated.

bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

MIC_ON : Enables the filter chain for voice when set to 1.

• 0: Filter chain is disabled.
• 1: Filter chain is enabled.

bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

DMA_EN : Enables the DMA.

• 0: DMA is disabled.
• 1: DMA is enabled.

bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

ENDCAL : 1: when the calibration is completed. The result of the calibration is written in the ADC_OFFSET register.
bits : 0 - 0 (1 bit)

BUSY : 1: during conversion.
bits : 1 - 1 (1 bit)

EOC : 1: when the conversion is completed.
bits : 2 - 2 (1 bit)

WDOG : If ENAB_COMP=1, this bit indicates the result of the conversion is between high and low threshold:

• 0: DATAOUT[31:0] is NOT between THRESHOLD_HI and THRESHOLD_LO values.
• 1: DATAOUT[31:0] is between THRESHOLD_HI and THRESHOLD_LO values.

bits : 3 - 3 (1 bit)

EN_DFMODE : Control the current in differential mode:

• 0: Differential mode with DC common mode current not nulled.
• 1: Differential mode with DC common mode current nulled.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

CHSEL : Select the input channel:

• 000b: All switches open.
• 001b: Single ended through ADC2 pin. InP=VREF (internal), InN=ADC2 pin.
• 010b: Single ended through ADC1 pin. InP=ADC1 pin, InN=VREF (internal).
• 011b: Differential ADC1 pin - ADC2 pin, InP=ADC1 pin, InN=ADC2 pin.
• 101b: Battery level detector. InP=0.6V (internal), InN=BLD.
• 110b: Short InN=InP=0.6V (internal).

bits : 1 - 3 (3 bit)

Enumeration:

End of enumeration elements list.

REFSEL : Set the VREF for single ended conversion:

• 00b: 0.0V.
• 01b: 0.4V.
• 10b: 0.6V.
• 11b: 1.2V.

bits : 4 - 5 (2 bit)

Enumeration:

End of enumeration elements list.

DECIM_RATE : Set the ADC resolution:

• 00b: Set the decimation factor to 200.
• 01b: Set the decimation factor to 100.
• 10b: Set the decimation factor to 64.
• 11b: Set the decimation factor to 32.

bits : 6 - 7 (2 bit)

Enumeration:

End of enumeration elements list.

PGASEL : Set the input attenuator value:

• 000b: Input attenuator at 0 dB.
• 001b: Input attenuator at 6.02 dB.
• 010b: Input attenuator at 9.54 dB.

bits : 8 - 9 (2 bit)

Enumeration:

End of enumeration elements list.

CONT : Enable the continuous conversion mode:

• 0: Single conversion.
• 1: Continuous conversion.

bits : 11 - 11 (1 bit)

Enumeration:

End of enumeration elements list.

ROUND16 : Result mapped on 32 or 16 bits:

• 0: Output result mapped to 32 bits.
• 1: Output result mapped to 16 bits.

bits : 17 - 17 (1 bit)

Enumeration:

End of enumeration elements list.

SKIP : It permits to bypass the filter comb to speed up the conversion for signal at low frequency:

• 0: Filter for comb not bypassed.
• 1: Filter for comb bypassed.

bits : 18 - 18 (1 bit)

Enumeration:

End of enumeration elements list.

DIG_FILT_CLK : Frequency clock selection value on GPIO0 when MIC_SEL=1:

• 0: 0.8 MHz.
• 1: 1.6 MHz.

bits : 20 - 20 (1 bit)

Enumeration:

End of enumeration elements list.

DIS_WKP_WAIT : Disable the wake-up timer before to start the conversion from input:

• 0: Do not disable the wake up time before conversion.
• 1: Disable the wake up time before conversion.

bits : 21 - 21 (1 bit)

Enumeration:

End of enumeration elements list.

MIC_SEL : Provides the clock on GPIO:

• 0: Do not provided any external clock source.
• 1: Provide clock source from GPIO.

bits : 22 - 22 (1 bit)

Enumeration:

End of enumeration elements list.

ENDCAL : 1: when the calibration is completed. Clear on register read.
bits : 0 - 0 (1 bit)

BUSY : 1: during conversion. Clear on register read if BUSY condition no more active.
bits : 1 - 1 (1 bit)

EOC : 1: when the conversion is completed. Clear on register read.
bits : 2 - 2 (1 bit)

WDOG : 1: when the data is within the thresholds. Clear on register read.
bits : 3 - 3 (1 bit)

ENDCAL : Interrupt mask for the end of calibration event:

• 0: Interrupt is enabled.
• 1: Interrupt is disabled.

bits : 0 - 0 (1 bit)

BUSY : Interrupt mask for the ADC busy event:

• 0: Interrupt is enabled.
• 1: Interrupt is disabled.

bits : 1 - 1 (1 bit)

EOC : Interrupt mask for the end of conversion event:

• 0: Interrupt is enabled.
• 1: Interrupt is disabled.

bits : 2 - 2 (1 bit)

WDOG : Interrupt mask for the within the threhsold event:

• 0: Interrupt is enabled.
• 1: Interrupt is disabled.

bits : 3 - 3 (1 bit)