CR

TFR

SR

RFR

TFTR

RFTR

DMAR

BRCR

IMSCR

RISR

MISR

ICR

SCR

THDDAT

THDSTA_FST_STD

TSUSTA_FST_STD

MCR

PE : I2C enable disable:

• 0: I2C disable.
• 1: I2C enable.

This bit when deasserted works as software reset for I2C peripheral.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

OM : Select the operating mode:

• 00b: Slave mode. The peripheral can only respond (transmit/receive) when addressed by a master device
• 01b: Master mode. The peripheral works in a multi-master system where itself cannot be addressed by another master device. It can only initiate a new transfer as master device.
• 10b: Master/slave mode. The peripheral works in a multi-master system where itself can be addressed by another master device, besides to initiate a transfer as master device.

bits : 1 - 2 (2 bit)

Enumeration:

End of enumeration elements list.

SAM : Slave addressing mode. SAM defines the slave addressing mode when the peripheral works in slave or master/slave mode. The received address is compared with the content of the register SCR.

• 0: 7-bit addressing mode.
• 1: 10-bit addressing mode.

bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

SM : Speed mode. SM defines the speed mode related to the serial bit rate:

• 0: Standard mode (up to 100 K/s).
• 1: Fast mode (up to 400 K/s).

bits : 4 - 5 (2 bit)

Enumeration:

End of enumeration elements list.

SGCM : Slave general call mode defines the operating mode of the slave controller when a general call is received. This setting does not affect the hardware general call that is always managed in transparent mode.

• 0: transparent mode, the slave receiver recognizes the general call but any action is taken by the hardware after the decoding of the message included in the Rx FIFO.
• 1: direct mode, the slave receiver recognizes the general call and executes directly (without software intervention) the related actions. Only the status code word is stored in the I2C_SR register for notification to the application.

bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

FTX : FTX flushes the transmit circuitry (FIFO, fsm). The configuration of the I2C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I2C clocks) and needs several system clock cycles before being completed. Upon completion, the I2C node (internal logic) clears this bit. The application must not access the Tx FIFO during the flushing operation and should poll on this bit waiting for completion.

• 0: Flush operation is completed (I2C controller clears the bit).
• 1: Flush operation is started and in progress (set by application).

bits : 7 - 7 (1 bit)

FRX : FRX flushes the receive circuitry (FIFO, fsm).The configuration of the I2C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I2C clocks) and needs several system clock cycles before to be completed. Upon completion, the I2C node (internal logic) clears this bit. The application must not access the Rx FIFO during the flushing operation and should poll on this bit waiting for the completion.

• 0: Flush operation is completed (I2C controller clears the bit).
• 1: Flush operation is started and in progress (set by application).

bits : 8 - 8 (1 bit)

DMA_TX_EN : Enables the DMA TX interface.

• 0: Idle state, the DMA TX interface is disabled.
• 1: Run state, the DMA TX interface is enabled.

On the completion of the DMA transfer, the DMA TX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time.
bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

DMA_RX_EN : Enables the DMA RX interface.

• 0: Idle state, the DMA RX interface is disabled.
• 1: Run state, the DMA RX interface is enabled.

On the completion of the DMA transfer, the DMA RX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time.
bits : 10 - 10 (1 bit)

Enumeration:

End of enumeration elements list.

FON : Filtering on sets the digital filters on the SDA, SCL line, according to the I2C bus requirements, when standard open-drain pads are used:

• 00b: No digital filters are inserted.
• 01b: Digital filters (filter 1 ck wide spikes) are inserted.
• 10b: Digital filters (filter 2 ck wide spikes) are inserted.
• 11b: Digital filters (filter 4 ck wide spikes) are inserted.

bits : 13 - 14 (2 bit)

Enumeration:

End of enumeration elements list.

FS_1 : Force stop enable bit. When set to 1b, the STOP condition is generated.

• 0: Force stop disabled.
• 1: Enable force stop.

bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

TDATA : Transmission Data. TDATA contains the payload related to a master write or read-from-slave operation to be written in the Tx FIFO. TDATA(0) is the first LSB bit transmitted over the I2C line.

In case of master write operation, the Tx FIFO shall be preloaded otherwise the I2C controller cannot start the operation until data are available.

In case of read-from-slave operation, when the slave is addressed, the interrupt RISR:RFSR bit is asserted and the CPU shall download the data in the FIFO. If the FIFO is empty and the I2C master is still requiring data, a new request (RISR:RFSE interrupt bit) is asserted to require additional data to the CPU. The slave controller stretches the I2C clock line when no data are available for transmission. Since the Tx FIFO could contain some pending data related to the previous transfer (the transfer length may be unknown to the slave controller), the Tx FIFO is self-flushed before asserting the I2C_RISR:RFSR bit. Upon completion of the read-from-slave operation the interrupt bit I2C_RISR:STD is asserted and the related status of the operation is stored in the I2C_SR register. In CPU mode, the FIFO management shall be based on the assertion of the interrupt bit RISR:TXFNE, related to the nearly-empty threshold.

In DMA mode, the single/burst requests are automatically executed based on the number of entries available in the TX FIFO and the related destination burst size programmed in the I2C_DMAR:DBSIZE_TX register field. The DMA requests are terminated at the end of the I2C read operation (notacknowledge received by the master) by a dummy last single/burst request.

bits : 0 - 7 (8 bit)

OP : Operation:

• 00b: MW: master write operation.
• 01b: MR: master read operation.
• 10b: WTS: write-to-slave operation.
• 11b: RFS: read-from-slave operation.

bits : 0 - 1 (2 bit)

Enumeration:

End of enumeration elements list.

STATUS : Controller status. Valid for the operations MW, MR, WTS RFS:

• 00b: NOP: No operation is in progress.
• 01b: ON_GOING: An operation is ongoing.
• 10b: OK: The operation (OP field) has been completed successfully.
• 11b: ABORT: The operation (OP field) has been aborted due to the occurrence of the event described in the CAUSE field.

bits : 2 - 3 (2 bit)

Enumeration:

End of enumeration elements list.

CAUSE : Abort cause. This field is valid only when the STATUS field contains the ABORT tag. Others: RESERVED.

• 000b: NACK_ADDR: The master receives a not-acknowledge after the transmission of the address. Valid for the operation MW, MR.
• 001b: NACK_DATA: The master receives a not-acknowledge during the data phase of a MW operation. Valid for the operation MW.
• 011b: ARB_LOST: The master loses the arbitration during a MW or MR operation. Valid for the operation MW, MR.
• 100b: BERR_START: Slave restarts, a START Condition occurs while the byte transfer is not terminated.
• 101b: BERR_STOP: Slave reset, a STOP Condition while the byte transfer is not terminated.
• 110b: OVFL: The slave receives a frame related to the WTS operation longer than the maximum size = 2047 bytes. In this case the slave device returns a NACK to complete the data transfer. Valid for WTS operation

bits : 4 - 6 (3 bit)

Enumeration:

End of enumeration elements list.

TYPE : Receive type. Valid only for the operation WTS:

• 00b: FRAME: The slave has received a normal frame.
• 01b: GCALL: The slave has received a general call. If the it I2C_CR:SGCM is set to 1, the general call is directly executed without software intervention and only the control code word is reported in FIFO (LENGTH =0).
• 10b: HW_GCALL: The slave has received a hardware general call.

bits : 7 - 8 (2 bit)

Enumeration:

End of enumeration elements list.

LENGTH : Transfer length. For an MR, WTS operation the LENGTH field defines the actual size of the subsequent payload, in terms of number of bytes. For an MW, RFS operation the LENGTH field defines the actual number of bytes transferred by the master/slave device. For a WTS operation if the transfer length exceeds 2047 bytes, the operation is stopped by the slave returning a NACK handshake and the flag OVFL is set. For an RFS operation if the transfer length exceeds 2047 bytes, the operation continues normally but the LENGTH field is reset to 0.
bits : 9 - 18 (10 bit)

DUALF : Dual flag (slave mode):

• 0: Received address matched with slave address (SA7).
• 1: Received address matched with dual slave address (DSA7).

Cleared by hardware after a Stop condition or repeated Start condition, bus error or when PE=0.
bits : 29 - 29 (1 bit)

Enumeration:

End of enumeration elements list.

RDATA : Receive data. RDATA contains the received payload, related to a master read or write-to-slave operation, to be read from the Rx FIFO. The RDATA(0) is the first LSB bit received over the I2C line. In case the FIFO is full, the I2C controller stretches automatically the I2C clock line until a new entry is available.

For a write-to-slave operation, when the slave is addressed, the interrupt I2C_RISR:WTSR bit is asserted for notification to the CPU. In CPU mode the FIFO management shall be based on the assertion of the interrupt bit I2C_RISR:RXFNF, related to the nearly-full threshold.

In DMA mode, the single requests are automatically executed based on the number of entries contained in the Rx FIFO.

bits : 0 - 7 (8 bit)

THRESH_TX : Threshold TX, contains the threshold value, in terms of number of bytes, of the Tx FIFO.

When the number of entries of the Tx FIFO is less or equal than the threshold value, the interrupt bit I2C_RISR:TXFNE is set in order to request the loading of data to the application.

bits : 0 - 9 (10 bit)

THRESH_RX : Threshold RX, contains the threshold value, in terms of number of bytes, of the Rx FIFO.

When the number of entries of the RX FIFO is greater than or equal to the threshold value, the interrupt bit RISR:RXFNF is set in order to request the download of received data to the application. The application shall download the received data based on the threshold. (RISR:RXFNF).

bits : 0 - 9 (10 bit)

DBSIZE_TX : Destination burst size. This register field is valid only if the BURST_TX bit is set to '1'. If burst size is smaller than the transaction length, only single request are generated.
bits : 8 - 10 (3 bit)

BURST_TX : Defines the type of DMA request generated by the DMA TX interface.

• 0: Single request mode. Transfers a single data (one byte) in the TX FIFO.
• 1: Burst request mode. Transfers a programmed burst of data according to DBSIZE_TX field.

When the burst mode is programmed, the DMA transfer can be completed by one or more single requests as required.
bits : 11 - 11 (1 bit)

BRCNT : Baud rate counter. BRCNT defines the counter value used to set up the I2C baud rate in standard and fast mode, when the peripheral is operating in master mode.
bits : 0 - 15 (16 bit)

TXFEM : TX FIFO empty mask. TXFEM enables the interrupt bit TXFE:

• 0: TXFE interrupt is disabled.
• 1: TXFE interrupt is enabled.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

TXFNEM : TX FIFO nearly empty mask. TXFNEM enables the interrupt bit TXFNE:

• 0: TXFNE interrupt is disabled.
• 1: TXFNE interrupt is enabled.

bits : 1 - 0 ( bit)

TXFFM : TX FIFO full mask. TXFFM enables the interrupt bit TXFF:

• 0: TXFF interrupt is disabled.
• 1: TXFF interrupt is enabled.

bits : 2 - 1 ( bit)

TXFOVRM : TX FIFO overrun mask. TXOVRM enables the interrupt bit TXOVR:

• 0: TXOVR interrupt is disabled.
• 1: TXOVR interrupt is enabled.

bits : 3 - 2 ( bit)

RXFEM : RX FIFO empty mask. RXFEM enables the interrupt bit RXFE:

• 0: RXFE interrupt is disabled.
• 1: RXFE interrupt is enabled.

bits : 4 - 3 ( bit)

RXFNFM : RX FIFO nearly full mask. RXNFM enables the interrupt bit RXNF:

• 0: RXNF interrupt is disabled.
• 1: RXNF interrupt is enabled

bits : 5 - 4 ( bit)

RXFFM : RX FIFO full mask. RXFFM enables the interrupt bit RXFF:

• 0: RXFF interrupt is disabled.
• 1: RXFF interrupt is enabled.

bits : 6 - 5 ( bit)

RFSRM : Read-from-Slave request mask. RFSRM enables the interrupt bit RFSR:

• 0: RFSR interrupt is disabled.
• 1: RFSR interrupt is enabled.

bits : 16 - 15 ( bit)

RFSEM : Read-from-Slave empty mask. RFSEM enables the interrupt bit RFSE:

• 0: RFSE interrupt is disabled.
• 1: RFSE interrupt is enabled.

bits : 17 - 16 ( bit)

WTSRM : Write-to-Slave request mask. WTSRM enables the interrupt bit WTSR:

• 0: WTSR interrupt is disabled.
• 1: WTSR interrupt is enabled.

bits : 18 - 17 ( bit)

MTDM : Master Transaction done mask. MTDM enables the interrupt bit MTD:

• 0: MTD interrupt is disabled.
• 1: MTD interrupt is enabled.

bits : 19 - 18 ( bit)

STDM : Slave Transaction done mask. STDM enables the interrupt bit STD:

• 0: STDM interrupt is disabled.
• 1: STDM interrupt is enabled.

bits : 20 - 19 ( bit)

MALM : Master Arbitration lost mask. MALM enables the interrupt bit MAL:

• 0: MAL interrupt is disabled.
• 1: MAL interrupt is enabled.

bits : 24 - 23 ( bit)

BERRM : Bus Error mask. BERRM enables the interrupt bit BERR:

• 0: BERR interrupt is disabled.
• 1: BERR interrupt is enabled.

bits : 25 - 24 ( bit)

MTDWSM : Master Transaction done without stop mask. MTDWSM enables the interrupt bit MTDWS:

• 0: MTDWS interrupt is disabled.
• 1: MTDWS interrupt is enabled.

bits : 28 - 27 ( bit)

TXFE : TX FIFO empty. TXFE is set when TX FIFO is empty. This bit is self-cleared by writing in TX FIFO.

• 0: TX FIFO is not empty.
• 1: TX FIFO is empty.

bits : 0 - 0 (1 bit)

TXFNE : TX FIFO nearly empty. TXFNE is set when the number of entries in TX FIFO is less than or equal to the threshold value programmed in the I2C_TFTR:THRESHOLD_TX register. It is self-cleared when the threshold level is over the programmed threshold.

• 0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.
• 1: Number of entries in TX FIFO less than or equal to the TFTR:THRESHOLD_TX register.

bits : 1 - 1 (1 bit)

TXFF : TX FIFO full. TXFF is set when a full condition occurs in TX FIFO. This bit is self-cleared when the TX FIFO is not full:

• 0: TX FIFO is not full.
• 1: TX FIFO is full.

bits : 2 - 2 (1 bit)

TXFOVR : TX FIFO overrun. TXFOVR is set when a write operation in TX FIFO is performed and TX FIFO is full. The application must avoid an overflow condition by a proper data flow control. Anyway in case of overrun, the application shall flush the transmitter (CR:FTX bit to set) because the TX FIFO content is corrupted (at least one word has been lost in FIFO). This interrupt is cleared by setting the related bit of the ICR register:

• 0: No overrun condition occurred in TX FIFO.
• 1: Overrun condition occurred in TX FIFO.

bits : 3 - 3 (1 bit)

RXFE : RX FIFO empty. RXFE is set when the RX FIFO is empty. This bit is self-cleared when the slave RX FIFO is not empty:

• 0: RX FIFO is not empty..
• 1: RX FIFO is empty..

bits : 4 - 4 (1 bit)

RXFNF : RX FIFO nearly full. RXFNF is set when the number of entries in RX FIFO is greater than or equal to the threshold value programmed in the RFTR:THRESHOLD_RX register. Its self-cleared when the threshold level is under the programmed threshold:

• 0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.
• 1: Number of entries in the RX FIFO greater than or equal to the RFTR:THRESHOLD_RX register.

bits : 5 - 5 (1 bit)

RXFF : RX FIFO full. RXFF is set when a full condition occurs in RX FIFO. This bit is self-cleared when the data are read from the RX FIFO.

• 0: RX FIFO is not full.
• 1: RX FIFO is full.

bits : 6 - 6 (1 bit)

LBR : Length number of bytes received. LBR is set in case of MR or WTS and when the number of bytes received is equal to the transaction length programmed in the MCR:LENGTH (master mode) or SMB_SCR:LENGTH (slave mode). On the assertion of this interrupt and when the bit CR:FRC_STRTCH is set, the hardware starts clock stretching, the CPU shall download the data byte (Command code, Byte Count, Data...) from RX FIFO, re-set the expected length of the transaction in SMB_SCR:LENGTH and clear the interrupt. When clearing this interrupt the hardware continues the transfer. This interrupt is cleared by setting the related bit of the ICR register.

• 0: Length number of bytes is not received.
• 1: Length number of bytes is received.

bits : 15 - 15 (1 bit)

RFSR : Read-from-slave request. RFSR is set when a read-from-slave "Slavetransmitter" request is received (I2C slave is addressed) from the I2C line. On the assertion of this interrupt the TX FIFO is flushed (pending data are cleared) and the CPU shall put the data in TX FIFO. This bit is self-cleared by writing data in FIFO. In case the FIFO is empty before the completion of the read operation, the RISR:RFSE interrupt bit is set.This interrupt is cleared by setting the related bit of the ICR register.

• 0: Read-from-slave request has been served.
• 1: Read-from-slave request is pending.

bits : 16 - 16 (1 bit)

RFSE : Read-from-Slave empty. RFSE is set when a read-from-slave operation is in progress and TX FIFO is empty. On the assertion of this interrupt, the CPU shall download in TX FIFO the data required for the slave operation. This bit is self-cleared by writing in TX FIFO. At the end of the read-from-slave operation this bit is cleared although the TX FIFO is empty.

• 0: TX FIFO is not empty.
• 1: TX FIFO is empty with the read-from-slave operation in progress.

bits : 17 - 17 (1 bit)

WTSR : Write-to-Slave request. WTSR is set when a write-to-slave operation is received (I2C slave is addressed) from the I2C line. This notification can be used by the application to program the DMA descriptor when required. This interrupt is cleared by setting the related bit of the ICR register:

• 0: No write-to-slave request pending.
• 1: Write-to-slave request is pending.

bits : 18 - 18 (1 bit)

MTD : Master Transaction done. MTD is set when a master operation (master write or master read) has been executed after a stop condition. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a master read operation) and clear this interrupt (transaction acknowledgment). A subsequent master operation can be issued (writing the MCR register) after the clearing of this interrupt. A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. This interrupt is cleared by setting the related bit of the ICR register.

• 0: Master transaction acknowledged.
• 1: Master transaction done (ready for acknowledgment).

bits : 19 - 19 (1 bit)

STD : Slave Transaction done. STD is set when a slave operation (write-to-slave or read-from-slave) has been executed. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a write-to-slave operation) and clear this interrupt (transaction acknowledgment). A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. A subsequent master operation can be issued (by writing the MCR register) after clearing this interrupt. This interrupt is cleared by setting the related bit of the ICR register:

• 0: Slave transaction acknowledged.
• 1: Slave transaction done (ready for acknowledgment).

bits : 20 - 20 (1 bit)

SAL : Slave Arbitration lost. SAL is set when the slave loses the arbitration during the data phase. A collision occurs when 2 devices transmit simultaneously 2 opposite values on the serial data line. The device that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, releases the bus and waits for the idle state (STOP condition received) on the bus line. The device which transmits the first unique zero wins the bus arbitration. This interrupt is cleared by setting the related bit of the ICR register.

• 0: No slave arbitration lost.
• 1: Slave arbitration lost.

bits : 23 - 23 (1 bit)

MAL : Master arbitration lost. MAL is set when the master loses the arbitration. The status code word in the SR contains a specific error tag (CAUSE field) for this error condition. A collision occurs when 2 stations transmit simultaneously 2 opposite values on the serial line. The station that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, leaves the bus and waits for the idle state (STOP condition received) on the bus line before retrying the same transaction. The station which transmits the first unique zero wins the bus arbitration. This interrupt is cleared by setting the related bit of the ICR register.

• 0: No master arbitration lost.
• 1: Master arbitration lost.

bits : 24 - 24 (1 bit)

BERR : Bus Error. BERR is set when an unexpected Start/Stop condition occurs during a transaction. The related actions are different, depending on the type of operation in progress.The status code word in the SR contains a specific error tag (CAUSE field) for this error condition. This interrupt is cleared by setting the related bit of the ICR register.

• 0: No bus error detection.
• 1: Bus error detection.

bits : 25 - 25 (1 bit)

MTDWS : Master transaction done without stop. MTDWS is set when a master operation (write or read) has been executed and a stop (MCR:P field) is not programmed. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a master read operation) and clear this interrupt (transaction acknowledgment). A subsequent master operation can be issued (by writing the MCR register) after clearing this interrupt. A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. This interrupt is cleared by setting the related bit of the ICR register:

• 0: Master transaction acknowledged.
• 1: Master transaction done (ready for acknowledgment) and stop is not applied into the I2C bus.

bits : 28 - 28 (1 bit)

TXFEMIS : TX FIFO empty masked interrupt status.

• 0: TX FIFO is not empty.
• 1: TX FIFO is empty.

bits : 0 - 0 (1 bit)

TXFNEMIS : TX FIFO nearly empty masked interrupt status.

• 0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.
• 1: Number of entries in TX FIFO less than or equal to the TFTR:THRESHOLD_TX register.

bits : 1 - 1 (1 bit)

TXFFMIS : Tx FIFO full masked interrupt status.

• 0: TX FIFO is not full.
• 1: TX FIFO is full.

bits : 2 - 2 (1 bit)

TXFOVRMIS : Tx FIFO overrun masked interrupt status.

• 0: No overrun condition occurred in TX FIFO.
• 1: Overrun condition occurred in TX FIFO.

bits : 3 - 3 (1 bit)

RXFEMIS : RX FIFO empty masked interrupt status.

• 0: RX FIFO is not empty.
• 1: RX FIFO is empty..

bits : 4 - 4 (1 bit)

RXFNFMIS : RX FIFO nearly full masked interrupt status.

• 0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.
• 1: Number of entries in the RX FIFO greater than or equal to the RFTR:THRESHOLD_RX register.

bits : 5 - 5 (1 bit)

RXFFMIS : RX FIFO full masked interrupt status.

• 0: RX FIFO is not full.
• 1: RX FIFO is full.

bits : 6 - 6 (1 bit)

LBRMIS : Length number of bytes received masked interrupt status.

• 0: Length number of bytes is not received.
• 1: Length number of bytes is received.

bits : 15 - 15 (1 bit)

RFSRMIS : Read-from-Slave request masked interrupt status.

• 0: Read-from-slave request has been served.
• 1: Read-from-slave request is pending.

bits : 16 - 16 (1 bit)

RFSEMIS : Read-from-Slave empty masked interrupt status.

• 0: TX FIFO is not empty.
• 1: TX FIFO is empty with the read-from-slave operation in progress.

bits : 17 - 17 (1 bit)

WTSRMIS : Write-to-Slave request masked interrupt status.

• 0: No write-to-slave request pending.
• 1: Write-to-slave request is pending.

bits : 18 - 18 (1 bit)

MTDMIS : Master Transaction done masked interrupt status.

• 0: Master transaction acknowledged.
• 1: Master transaction done (ready for acknowledgment).

bits : 19 - 19 (1 bit)

STDMIS : Slave Transaction done masked interrupt status.

• 0: Slave transaction acknowledged.
• 1: Slave transaction done (ready for acknowledgment).

bits : 20 - 20 (1 bit)

SALMIS : Slave Arbitration lost masked interrupt status.

• 0: No slave arbitration lost.
• 1: Slave arbitration lost.

bits : 23 - 23 (1 bit)

MALMIS : Master Arbitration lost masked interrupt status.

• 0: No master arbitration lost.
• 1: Master arbitration lost.

bits : 24 - 24 (1 bit)

BERRMIS : Bus Error masked interrupt status.

• 0: No bus error detection.
• 1: Bus error detection.

bits : 25 - 25 (1 bit)

MTDWSMIS : Master Transaction done without stop masked interrupt status.

• 0: Master transaction acknowledged.
• 1: Master transaction done (ready for acknowledgment) and stop is not applied into the I2C bus.

bits : 28 - 28 (1 bit)

TIMEOUTMIS : Timeout or Tlow error masked interrupt status.

• 0: No timeout error.
• 1: SCL remained LOW for 25 ms (Timeout).

bits : 30 - 30 (1 bit)

TXFOVRIC : Tx FIFO overrun interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 3 - 3 (1 bit)

LBRIC : Length number of bytes received interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 15 - 15 (1 bit)

RFSRIC : Read-from-Slave request interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 16 - 16 (1 bit)

RFSEIC : Read-from-Slave empty interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 17 - 17 (1 bit)

WTSRIC : Write-to-Slave request interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 18 - 18 (1 bit)

MTDIC : Master Transaction done interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 19 - 19 (1 bit)

STDIC : Slave Transaction done interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 20 - 20 (1 bit)

SALIC : Slave Arbitration lost interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 23 - 23 (1 bit)

MALIC : Master Arbitration lost interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 24 - 24 (1 bit)

BERRIC : Bus Error interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 25 - 25 (1 bit)

MTDWSIC : Master Transaction done without stop interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 28 - 28 (1 bit)

TIMEOUTIC : Timeout or Tlow error interrupt clear.

• 0: Has no effect.
• 1: Clears interrupt pending.

bits : 30 - 30 (1 bit)

SA7 : Slave address 7-bit. SA7 includes the slave address 7-bit or the LSB bits of the slave address 10-bit
bits : 0 - 6 (7 bit)

ESA10 : Extended slave address 10-bit. ESA10 includes the extension (MSB bits) to the SA7 register field in case of slave addressing mode set to 10-bit
bits : 7 - 9 (3 bit)

SLSU : Slave data setup time. SLSU defines the data setup time after SCL clock stretching in terms of i2c_clk cycles. Data setup time is actually equal to SLSU-1 clock cycles. The typical values for i2c_clk of 16 MHz are SLSU = 5 in standard mode and SLSU = 3 in fast modes.
bits : 16 - 31 (16 bit)

THDDAT : Hold time data value. In master or slave mode, when the I2C controller detects a falling edge in the SCL line, the counter, which is loaded by the THDDAT, is launched. Once the THDDAT value is reached, the data is transferred.
bits : 0 - 8 (9 bit)

THDSTA_STD : Hold time start condition value for standard mode. When the start condition is asserted, the decimeter loads the value of THDSTA_STD for standard mode, once the THDSTA_STD value is reached, the SCL line asserts low.
bits : 0 - 8 (9 bit)

THDSTA_FST : Hold time start condition value for fast mode. When the start condition is asserted, the decimeter loads the value of THDSTA_FST for fast mode, once the THDSTA_FST value is reached, the SCL line assert slow.
bits : 16 - 24 (9 bit)

TSUSTA_STD : Setup time start condition value for standard mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_STD according to standard mode. Once the counter is expired, the start condition is generated.
bits : 0 - 8 (9 bit)

TSUSTA_FST : Setup time start condition value for fast mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_FST according to fast mode. Once the counter is expired the start condition is generated.
bits : 16 - 24 (9 bit)

OP : Operation

• 0: Indicates a master write operation.
• 1: Indicates a master read operation.

bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

A7 : Address. Includes the 7-bit address or the LSB bits of the10-bit address used to initiate the current transaction
bits : 1 - 7 (7 bit)

EA10 : Extended address. Includes the extension (MSB bits) of the field A7 used to initiate the current transaction
bits : 8 - 10 (3 bit)

SB : Start byte:

• 0: The start byte procedure is not applied to the current transaction.
• 1: The start byte procedure is prefixed to the current transaction.

bits : 11 - 11 (1 bit)

AM : Address type:

• 00b: The transaction is initiated by a general call command. In this case the fields OP, A7, EA10 are "don't care".
• 01b: The transaction is initiated by the 7-bit address included in the A7 field.
• 10b: The transaction is initiated by the 10-bit address included in the EA10 and A7 fields.

bits : 12 - 13 (2 bit)

Enumeration:

End of enumeration elements list.

P : Stop condition:

• 0: The current transaction is not terminated by a STOP condition. A repeated START condition is generated on the next operation which is required to avoid to stall the I2C line.
• 1: The current transaction is terminated by a STOP condition.

bits : 14 - 14 (1 bit)

LENGTH : Transaction length. Defines the length, in terms of the number of bytes to be transmitted (MW) or received (MR). In case of write operation, the payload is stored in the Tx FIFO. A transaction can be larger than the Tx FIFO size. In case of read operation the length refers to the number of bytes to be received before generating a not-acknowledge response. A transaction can be larger than the Rx FIFO size. The I2C clock line is stretched low until the data in Rx FIFO are consumed.
bits : 15 - 25 (11 bit)