ISR

IFCR

GIF0 : Channel 0 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 0.
• 1: A TE, HT or TC event occurred on channel 0.

bits : 0 - 0 (1 bit)

TCIF0 : Channel 0 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 0.
• 1: A transfer complete (TC) occurred on channel 0.

bits : 1 - 1 (1 bit)

HTIF0 : Channel 0 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 0.
• 1: A half transfer (HT) event occurred on channel 0.

bits : 2 - 2 (1 bit)

TEIF0 : Channel 0 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 0.
• 1: A transfer error (TE) occurred on channel 0.

bits : 3 - 3 (1 bit)

GIF1 : Channel 1 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 1.
• 1: A TE, HT or TC event occurred on channel 1.

bits : 4 - 4 (1 bit)

TCIF1 : Channel 1 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 1.
• 1: A transfer complete (TC) occurred on channel 1.

bits : 5 - 5 (1 bit)

HTIF1 : Channel 1 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 1.
• 1: A half transfer (HT) event occurred on channel 1.

bits : 6 - 6 (1 bit)

TEIF1 : Channel 1 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 1.
• 1: A transfer error (TE) occurred on channel 1.

bits : 7 - 7 (1 bit)

GIF2 : Channel 2 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 2.
• 1: A TE, HT or TC event occurred on channel 2.

bits : 8 - 8 (1 bit)

TCIF2 : Channel 2 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 2.
• 1: A transfer complete (TC) occurred on channel 2.

bits : 9 - 9 (1 bit)

HTIF2 : Channel 2 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 2.
• 1: A half transfer (HT) event occurred on channel 2.

bits : 10 - 10 (1 bit)

TEIF2 : Channel 2 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 2.
• 1: A transfer error (TE) occurred on channel 2.

bits : 11 - 11 (1 bit)

GIF3 : Channel 3 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 3.
• 1: A TE, HT or TC event occurred on channel 3.

bits : 12 - 12 (1 bit)

TCIF3 : Channel 3 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 3.
• 1: A transfer complete (TC) occurred on channel 3.

bits : 13 - 13 (1 bit)

HTIF3 : Channel 3 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 3.
• 1: A half transfer (HT) event occurred on channel 3.

bits : 14 - 14 (1 bit)

TEIF3 : Channel 3 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 3.
• 1: A transfer error (TE) occurred on channel 3.

bits : 15 - 15 (1 bit)

GIF4 : Channel 4 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 4.
• 1: A TE, HT or TC event occurred on channel 4.

bits : 16 - 16 (1 bit)

TCIF4 : Channel 4 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 4.
• 1: A transfer complete (TC) occurred on channel 4.

bits : 17 - 17 (1 bit)

HTIF4 : Channel 4 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 4.
• 1: A half transfer (HT) event occurred on channel 4.

bits : 18 - 18 (1 bit)

TEIF4 : Channel 4 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 4.
• 1: A transfer error (TE) occurred on channel 4.

bits : 19 - 19 (1 bit)

GIF5 : Channel 5 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 5.
• 1: A TE, HT or TC event occurred on channel 5.

bits : 20 - 20 (1 bit)

TCIF5 : Channel 5 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 5.
• 1: A transfer complete (TC) occurred on channel 5.

bits : 21 - 21 (1 bit)

HTIF5 : Channel 5 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 5.
• 1: A half transfer (HT) event occurred on channel 5.

bits : 22 - 22 (1 bit)

TEIF5 : Channel 5 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 5.
• 1: A transfer error (TE) occurred on channel 5.

bits : 23 - 23 (1 bit)

GIF6 : Channel 6 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 6.
• 1: A TE, HT or TC event occurred on channel 6.

bits : 24 - 24 (1 bit)

TCIF6 : Channel 6 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 6.
• 1: A transfer complete (TC) occurred on channel 6.

bits : 25 - 25 (1 bit)

HTIF6 : Channel 6 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 6.
• 1: A half transfer (HT) event occurred on channel 6.

bits : 26 - 26 (1 bit)

TEIF6 : Channel 6 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 6.
• 1: A transfer error (TE) occurred on channel 6.

bits : 27 - 27 (1 bit)

GIF7 : Channel 7 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No TE, HT or TC event on channel 7.
• 1: A TE, HT or TC event occurred on channel 7.

bits : 28 - 28 (1 bit)

TCIF7 : Channel 7 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer complete (TC) on channel 7.
• 1: A transfer complete (TC) occurred on channel 7.

bits : 29 - 29 (1 bit)

HTIF7 : Channel 7 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No half transfer (HT) event on channel 7.
• 1: A half transfer (HT) event occurred on channel 7.

bits : 30 - 30 (1 bit)

TEIF7 : Channel 7 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

• 0: No transfer error (TE) event on channel 7.
• 1: A transfer error (TE) occurred on channel 7.

bits : 31 - 31 (1 bit)

CGIF0 : Channel 0 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 0 - 0 (1 bit)

CTCIF0 : Channel 0 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 1 - 1 (1 bit)

CHTIF0 : Channel 0 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 2 - 2 (1 bit)

CTEIF0 : Channel 0 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 3 - 3 (1 bit)

CGIF1 : Channel 1 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 4 - 4 (1 bit)

CTCIF1 : Channel 1 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 5 - 5 (1 bit)

CHTIF1 : Channel 1 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 6 - 6 (1 bit)

CTEIF1 : Channel 1 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 7 - 7 (1 bit)

CGIF2 : Channel 2 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 8 - 8 (1 bit)

CTCIF2 : Channel 2 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 9 - 9 (1 bit)

CHTIF2 : Channel 2 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 10 - 10 (1 bit)

CTEIF2 : Channel 2 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 11 - 11 (1 bit)

CGIF3 : Channel 3 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 12 - 12 (1 bit)

CTCIF3 : Channel 3 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 13 - 13 (1 bit)

CHTIF3 : Channel 3 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 14 - 14 (1 bit)

CTEIF3 : Channel 3 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 15 - 15 (1 bit)

CGIF4 : Channel 4 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 16 - 16 (1 bit)

CTCIF4 : Channel 4 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 17 - 17 (1 bit)

CHTIF4 : Channel 4 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 18 - 18 (1 bit)

CTEIF4 : Channel 4 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 19 - 19 (1 bit)

CGIF5 : Channel 5 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 20 - 20 (1 bit)

CTCIF5 : Channel 5 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 21 - 21 (1 bit)

CHTIF5 : Channel 5 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 22 - 22 (1 bit)

CTEIF5 : Channel 5 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 23 - 23 (1 bit)

CGIF6 : Channel 6 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 24 - 24 (1 bit)

CTCIF6 : Channel 6 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 25 - 25 (1 bit)

CHTIF6 : Channel 6 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 26 - 26 (1 bit)

CTEIF6 : Channel 6 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 27 - 27 (1 bit)

CGIF7 : Channel 7 global interrupt flag. This bit is set by software.

• 0: No effect.
• 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

bits : 28 - 28 (1 bit)

CTCIF7 : Channel 7 transfer complete flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TCIF flag in the ISR register.

bits : 29 - 29 (1 bit)

CHTIF7 : Channel 7 half transfer flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding HTIF flag in the ISR register.

bits : 30 - 30 (1 bit)

CTEIF7 : Channel 7 transfer error flag. This bit is set by software.

• 0: No effect.
• 1: Clears the corresponding TEIF flag in the ISR register.

bits : 31 - 31 (1 bit)