CCR

CNDTR

CPAR

CMAR

EN : DMA channel enable.

• 0: DMA channel disabled.
• 1: DMA channel enabled.

bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCIE : Transfer complete interrupt enable.

• 0: TC interrupt disabled.
• 1: TC interrupt enabled.

bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HTIE : Half transfer interrupt enable.

• 0: HT interrupt disabled.
• 1: HT interrupt enabled.

bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEIE : Transfer error interrupt enable.

• 0: TE interrupt disabled.
• 1: TE interrupt enabled.

bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIR : Data transfer direction.

• 0: Read from peripheral.
• 1: Read from memory.

bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CIRC : Circular mode.

• 0: Circular mode disabled.
• 1: Circular mode enabled.

bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINC : Peripheral increment mode.

• 0: Peripheral increment disabled.
• 1: Peripheral increment enabled.

bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MINC : Memory increment mode.

• 0: Memory increment disabled.
• 1: Memory increment enabled.

bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSIZE : Peripheral size.

• 00b: Size 8 bits.
• 01b: Size 16 bits.
• 10b: Size 32 bits.

bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSIZE : Memory size.

• 00b: Size 8 bits.
• 01b: Size 16 bits.
• 10b: Size 32 bits.

bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PL : Channel priority level.

• 00b: Low priority.
• 01b: Medium priority.
• 10b: High priority.
• 11b: Very high priority.

bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MEM2MEM : Memory to memory mode.

• 0: Memory to memory mode disabled.
• 0: Memory to memory mode enabled.

bits : 14 - 14 (1 bit)
access : read-write

RESERVED1 : Reserved
bits : 15 - 31 (17 bit)
access : read-only

NDT : Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED1 : Reserved
bits : 16 - 31 (16 bit)
access : read-only

PA : Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
access : read-write

MA : Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
access : read-write