CR

SR

VAL

DIS : Set the state of the random number generator.

• 0: RNG is enable.
• 1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block.

bits : 2 - 2 (1 bit)
access : read-write

TST_CLK : RNG test clock bit. Writing this bit with 1b starts the logic that detects the presence of the CLK. Then wait (with a timeout of at least four RNGCLK cycles) for REVCLK = 1b in SR register. If REVCLK = 0b after timeout elapsed, it means that RNGCLK is not present and reading VAL register will trigger an AHB error response. For security reason, software should check before reading random values that the RNGCLK is present.
bits : 3 - 3 (1 bit)
access : read-write

RDY : New random value ready.

• 0: The RNG_VAL register value is not yet valid. If performing a read access to VAL, the host will be put on hold (by wait-states insertion on the AHB bus) until a random value is available.
• 1: The VAL register contains a valid random number.

This bit remains at 0 when the RNG is disabled (RNGDIS bit = 1b in CR)
bits : 0 - 0 (1 bit)
access : read-only

REVCLK : REVCLK clock reveal bit. A write with 1b to bit TSTCLK in CR resets this bit. If the RNGCLK is present, this bit will be 1b after four RNGCLK cycles after the end of the write to RNG_CR.If REVCLK = 0b after this period, it means the RNGCLK is not present and reading VAL will trigger a AHB error response.
bits : 1 - 1 (1 bit)
access : read-write

FAULT : Fault reveal bit. This bit is set by hardware when a faulty sequence of bits occurs. The faulty sequences are:

• 0: Sequence of more than 32 consecutive bits of same value (0b or 1b).
• 1: Sequence of more than 16 consecutive alternation of 0b and 1b (010101...01b).

Writing this bit:

• 0: No effect.
• 1: Clear the bit.

bits : 2 - 2 (1 bit)
access : read-write