\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Commands for the module
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status interrupts (unmasked)
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDDONE : Command is done.
bits : 0 - 0 (1 bit)
Enumeration:
1 : IRQ_PENDING
Irq pending
0 : IRQ_NOT_PENDING
Irq not pending
End of enumeration elements list.
CMDSTART : Command is started.
bits : 1 - 0 ( bit)
CMDERR : Command written while BUSY
bits : 2 - 1 ( bit)
ILLCMD : Illegal command written
bits : 3 - 2 ( bit)
READOK : Mass read was OK.
bits : 4 - 3 ( bit)
FLNREADY : Flash not ready (sleep).
bits : 5 - 4 ( bit)
Indicates the last usable address of the main Flash
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Address for programming Flash, will auto-increment
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFSR register needed for check after MASS READ command
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Trimming values for Flash erase/modify sequences
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Trimming values for Flash erase/modify sequences
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Trimming values for Flash wake-up sequence
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configure the wrapper
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Program cycle data
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Program cycle data
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Program cycle data
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Program cycle data
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Flash status interrupt (masked)
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDDONE : Command is done. 1: clear the interrupt pending bit.
bits : 0 - 0 (1 bit)
Enumeration:
1 : IRQ_PENDING
Irq pending
0 : IRQ_NOT_PENDING
Irq not pending
End of enumeration elements list.
CMDSTART : Command is started. 1: clear the interrupt pending bit.
bits : 1 - 0 ( bit)
CMDERR : Command written while BUSY. 1: clear the interrupt pending bit.
bits : 2 - 1 ( bit)
ILLCMD : Illegal command written. 1: clear the interrupt pending bit.
bits : 3 - 2 ( bit)
READOK : Mass read was OK. 1: clear the interrupt pending bit.
bits : 4 - 3 ( bit)
FLNREADY : Flash not ready (sleep). 1: clear the interrupt pending bit.
bits : 5 - 4 ( bit)
Mask for interrupts
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDDONE : Command is done.
bits : 0 - 0 (1 bit)
Enumeration:
1 : IRQ_PENDING
Irq pending
0 : IRQ_NOT_PENDING
Irq not pending
End of enumeration elements list.
CMDSTART : Command is started.
bits : 1 - 0 ( bit)
CMDERR : Command written while BUSY
bits : 2 - 1 ( bit)
ILLCMD : Illegal command written
bits : 3 - 2 ( bit)
READOK : Mass read was OK.
bits : 4 - 3 ( bit)
FLNREADY : Flash not ready (sleep).
bits : 5 - 4 ( bit)
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