\n

SYSTEM_CONTROLLER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WKP_IO_IS

SLEEPIO_OUT

SLEEPIO_DS

SLEEPIO_PE

WKP_IO_IE

CTRL

SLEEPIO_OEN


WKP_IO_IS

Level selection for wakeup IO (1 bit for IO) IO[13:9].


address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKP_IO_IS WKP_IO_IS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SLEEPIO_OUT

IO data output value register for low power modes. It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.


address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEPIO_OUT SLEEPIO_OUT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SLEEPIO_DS

IO drive strength control register for low power modes. It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.


address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEPIO_DS SLEEPIO_DS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SLEEPIO_PE

IO pull enable register for low power modes. It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.


address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEPIO_PE SLEEPIO_PE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

WKP_IO_IE

Enables the IO that wakes up the device (1 bit for IO) IO[13:9].


address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKP_IO_IE WKP_IO_IE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTRL

XO frequency indication to provide by the application
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MHZ32_SEL

MHZ32_SEL : Indicates the crystal frequency used in the application.


bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MHz16

16 MHz is selected

1 : MHz32

32 MHz is selected

End of enumeration elements list.


SLEEPIO_OEN

IO output enable register for low power modes. It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.


address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEPIO_OEN SLEEPIO_OEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.