\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Result of the conversion negligeble.
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Result of the conversion in two complement format.
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Offset for correction of converted data
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC control register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ON : Starts ADC analog subsystem. This bit must be set before starting a conversion.
Enumeration:
0 : OFF
ADC analog part disable
1 : ON
ADC analog part enable
End of enumeration elements list.
CALEN : Enables the calibration phase when set to 1. This bit is cleared and the calibration is disabled by setting the RSTADCCALEN bit.
bits : 1 - 1 (1 bit)
Enumeration:
0 : CAL_OFF
ADC automatic calibration disable
1 : CAL_ON
ADC automatic calibration enable
End of enumeration elements list.
SWSTART : Starts the ADC conversion phase when set.
bits : 2 - 2 (1 bit)
Enumeration:
1 : START
Starts the ADC conversion phase when set.
End of enumeration elements list.
RESET : Reset all the ADC APB registers when set.
bits : 3 - 3 (1 bit)
Enumeration:
1 : RESET
Reset all the registers content
End of enumeration elements list.
STOP : Permits to stop the continuous conversion.
Enumeration:
1 : STOP
Stop the continuous mode conversion
End of enumeration elements list.
ENAB_COMP : Enables the window comparator when set to 1. WDOG flag is ADC_SR register is set if the converted value is between ADCTHRESHOLD_HI and ADCTHRESHOLD_LO value.
bits : 5 - 5 (1 bit)
RSTCALEN : Disable the calibration phase when set to 1. This bit has to be set to disable the calibration each time calibration is enabled.
bits : 6 - 6 (1 bit)
Enumeration:
1 : RESET
Reset the ADCCALEN bit. Disable the automatic calibration when it is enabled
End of enumeration elements list.
AUTO_OFFSET : Enables the update of ADC_OFFSET register.
Enumeration:
0 : CAL_OFF
ADC automatic calibration disable
1 : CAL_ON
ADC automatic calibration enable
End of enumeration elements list.
MIC_ON : Enables the filter chain for voice when set to 1.
Enumeration:
0 : MIC_OFF
Filter chain disable
1 : MIC_ON
Filter chain enable
End of enumeration elements list.
DMA_EN : Enables the DMA.
Enumeration:
0 : DMA_OFF
ADC DMA disable
1 : DMA_ON
ADC DMA enable
End of enumeration elements list.
ADC status register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDCAL : 1: when the calibration is completed. The result of the calibration is written in the ADC_OFFSET register.
bits : 0 - 0 (1 bit)
BUSY : 1: during conversion.
bits : 1 - 1 (1 bit)
EOC : 1: when the conversion is completed.
bits : 2 - 2 (1 bit)
WDOG : If ENAB_COMP=1, this bit indicates the result of the conversion is between high and low threshold:
High threshold for window comparator
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low threshold for window comparator
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN_DFMODE : Control the current in differential mode:
Enumeration:
0 : DFMODE_OFF
Differential mode with DC common mode current not nulled
1 : DFMODE_ON
Differential mode with DC common mode current nulled
End of enumeration elements list.
CHSEL : Select the input channel:
Enumeration:
0 : ALL_SWITCH_OPEN
All switch open
1 : SINGLE_VINP
Single ended InP=ANATEST2 pin, InN=VREF (internal)
2 : SINGLE_VINN
Single ended InN=ANATEST3 pin, InP=VREF (internal)
3 : DIFF_INP_INN
Differential InP=ANATEST2 pin, InN=ANATEST3 pin
4 : TEMP_SENS
InP=VTEMPSENS (internal), InN=0.6V (internal)
5 : BATT_SENS
InP=VBATSENS (internal), InN=0.6V (internal)
6 : SHORT
InP=InN=0.6V (internal)
End of enumeration elements list.
REFSEL : Set the VREF for single ended conversion:
Enumeration:
3 : RESEL_0V0
Set the VREF at 0.0 V
2 : RESEL_0V6
Set the VREF at 0.6 V
End of enumeration elements list.
OSR : Set the ADC resolution:
Enumeration:
0 : OSR_200
Set the oversampling ratio to 200
1 : OSR_100
Set the oversampling ratio to 100
2 : OSR_64
Set the oversampling ratio to 64
3 : OSR_32
Set the oversampling ratio to 32
End of enumeration elements list.
PGASEL : Set the input attenuator value:
Enumeration:
0 : IN_ATT_0dB0
Input attenuator at 0 dB
1 : IN_ATT_6dB02
Input attenuator at 6.02 dB
2 : IN_ATT_9dB54
Input attenuator at 9.54 dB
End of enumeration elements list.
CONT : Enable the continuous conversion mode:
Enumeration:
0 : SINGLE
Single conversion mode
1 : CONT
Continuous conversion mode
End of enumeration elements list.
SKIP : It permits to bypass the filter comb to speed up the conversion for signal at low frequency:
Enumeration:
0 : FILTER_OFF
Filter for comb not bypassed
1 : FILTER_ON
Filter for comb bypassed
End of enumeration elements list.
DIG_FILT_CLK : Frequency clock selection value on GPIO0 when MIC_SEL=1:
Enumeration:
0 : CLK_0MHz8
Frequency clock to 0.8 MHz
1 : CLK_1MHz6
Frequency clock to 1.6 MHz
End of enumeration elements list.
DIS_WKP_WAIT : Disable the wake-up timer before to start the conversion from input:
Enumeration:
0 : ENABLE
Do not disable the wake up time before conversion
1 : DISABLE
Disable the wake up time before conversion
End of enumeration elements list.
MIC_SEL : Provides the clock on GPIO:
Enumeration:
0 : DISABLE
Do not provided any external clock source
1 : ENABLE
Provide clock source from GPIO
End of enumeration elements list.
IRQ masked status register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENDCAL : 1: when the calibration is completed. Clear on register read.
bits : 0 - 0 (1 bit)
BUSY : 1: during conversion. Clear on register read if BUSY condition no more active.
bits : 1 - 1 (1 bit)
EOC : 1: when the conversion is completed. Clear on register read.
bits : 2 - 2 (1 bit)
WDOG : 1: when the data is within the thresholds. Clear on register read.
bits : 3 - 3 (1 bit)
It sets the mask for ADC interrupt
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDCAL : Interrupt mask for the end of calibration event:
BUSY : Interrupt mask for the ADC busy event:
EOC : Interrupt mask for the end of conversion event:
WDOG : Interrupt mask for the within the threhsold event:
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