\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Control clock and reset of SOC
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART_CKDIV : UART baud rate clock setting from 1 to 16 MHz according to the formula 16 / (n + 1) MHz.
bits : 10 - 13 (4 bit)
access : read-write
Identification information of the device
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV : Cut revision
bits : 0 - 3 (4 bit)
access : read-only
VERSION : Cut version
bits : 4 - 7 (4 bit)
access : read-only
PRODUCT : Product
bits : 8 - 11 (4 bit)
access : read-only
Enable or gates the APB clock of the peripherals
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO : GPIO clock
bits : 0 - 0 (1 bit)
access : read-write
NVM : Flash controller clock
bits : 1 - 1 (1 bit)
access : read-write
SYSCTRL : System controller clock
bits : 2 - 2 (1 bit)
access : read-write
UART : UART clock
bits : 3 - 3 (1 bit)
access : read-write
SPI : SPI clock
bits : 4 - 4 (1 bit)
access : read-write
WDOG : Watchdog clock
bits : 7 - 7 (1 bit)
access : read-write
ADC : ADC clock
bits : 8 - 8 (1 bit)
access : read-write
I2C1 : I2C1 clock
bits : 9 - 9 (1 bit)
access : read-write
I2C2 : I2C2 clock
bits : 10 - 10 (1 bit)
access : read-write
MFT1 : MFT1 clock
bits : 11 - 11 (1 bit)
access : read-write
MFT2 : MFT2 clock
bits : 12 - 12 (1 bit)
access : read-write
RTC : RTC clock
bits : 13 - 13 (1 bit)
access : read-write
DMA : DMA AHB clock
bits : 16 - 16 (1 bit)
access : read-write
RNG : RNG AHB clock
bits : 17 - 17 (1 bit)
access : read-write
PKA : PKA AHB clock and RAM
bits : 18 - 19 (2 bit)
access : read-write
DMA config
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_CH0 : Select ADC on DMA channel 0 instead of peripheral
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : enable
enable
0 : disable
disable
End of enumeration elements list.
ADC_CH1 : Select ADC on DMA channel 1 instead of peripheral
bits : 1 - 0 ( bit)
ADC_CH2 : Select ADC on DMA channel 2 instead of peripheral
bits : 2 - 1 ( bit)
ADC_CH3 : Select ADC on DMA channel 3 instead of peripheral
bits : 3 - 2 ( bit)
ADC_CH4 : Select ADC on DMA channel 4 instead of peripheral
bits : 4 - 3 ( bit)
ADC_CH5 : Select ADC on DMA channel 5 instead of peripheral
bits : 5 - 4 ( bit)
ADC_CH6 : Select ADC on DMA channel 6 instead of peripheral
bits : 6 - 5 ( bit)
ADC_CH7 : Select ADC on DMA channel 7 instead of peripheral
bits : 7 - 6 ( bit)
Indicates the reset reason from Cortex-M0
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSREQ : Reset caused by Cortex-M0 debug asserting SYSRESETREQ
bits : 1 - 1 (1 bit)
access : read-only
WDG : Reset caused by assertion of watchdog reset
bits : 2 - 2 (1 bit)
access : read-only
LOCKUP : Reset caused by Cortex-M0 asserting LOCKUP signal
bits : 3 - 3 (1 bit)
access : read-only
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