\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
DMA channel configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA channel enable.
Enumeration:
0 : DISABLE
DMA channel disable
1 : ENABLE
DMA channel enable
End of enumeration elements list.
TCIE : Transfer complete interrupt enable.
Enumeration:
0 : DISABLE
Interrupt source disable
1 : ENABLE
Interrupt source enable
End of enumeration elements list.
HTIE : Half transfer interrupt enable.
Enumeration:
0 : DISABLE
Interrupt source disable
1 : ENABLE
Interrupt source enable
End of enumeration elements list.
TEIE : Transfer error interrupt enable.
Enumeration:
0 : DISABLE
Interrupt source disable
1 : ENABLE
Interrupt source enable
End of enumeration elements list.
DIR : Data transfer direction.
Enumeration:
0 : FROM_PERIPHERAL
Read from peripheral
1 : FROM_MEMORY
Read from memory
End of enumeration elements list.
CIRC : Circular mode.
Enumeration:
0 : DISABLE
Circular mode disable
1 : ENABLE
Circular mode enable
End of enumeration elements list.
PINC : Peripheral increment mode.
Enumeration:
0 : DISABLE
Peripheral increment disable
1 : ENABLE
Peripheral increment enable
End of enumeration elements list.
MINC : Memory increment mode.
Enumeration:
0 : DISABLE
Memory increment disable
1 : ENABLE
Memory increment enable
End of enumeration elements list.
PSIZE : Peripheral size.
Enumeration:
0 : SIZE8BIT
Size 8 bits
1 : SIZE16BIT
Size 16 bits
2 : SIZE32BIT
Size 32 bits
End of enumeration elements list.
MSIZE : Memory size.
Enumeration:
0 : SIZE8BIT
Size 8 bits
1 : SIZE16BIT
Size 16 bits
2 : SIZE32BIT
Size 32 bits
End of enumeration elements list.
PL : Channel priority level.
Enumeration:
0 : LOW
Low priority
1 : MEDIUM
Medium priority
2 : HIGH
High priority
3 : VERY_HIGH
Very high priority
End of enumeration elements list.
MEM2MEM : Memory to memory mode.
RESERVED1 : Reserved
bits : 15 - 31 (17 bit)
access : read-only
DMA channel number of data register.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED1 : Reserved
bits : 16 - 31 (16 bit)
access : read-only
DMA channel peripheral address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
access : read-write
DMA channel memory address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
access : read-write
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