RNG

Registers

RNG configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIS : Set the state of the random number generator.

0: RNG is enable.
1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block.

bits : 2 - 2 (1 bit)
access : read-write

RNG status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDY : New random value ready.

0: The RNG_VAL register value is not yet valid. If performing a read access to VAL, the host will be put on hold (by wait-states insertion on the AHB bus) until a random value is available.
1: The VAL register contains a valid random number.

This bit remains at 0 when the RNG is disabled (RNGDIS bit = 1b in CR)
bits : 0 - 0 (1 bit)
access : read-only

RNG 16 bit random value
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

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