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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

APBRSTR

APB2RSTR

APB1RSTR

AHBENR

APB2ENR

APB1ENR

AHBLPENR

AHB2LPENR

AHB1LPENR

CSR

ICSCR

CFGR

CIR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIRDY MSION MSIRDY HSEON HSERDY HSEBYP PLLON PLLRDY CSSON RTCPRE

HSION : HSION
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : HSIRDY
bits : 1 - 1 (1 bit)
access : read-only

MSION : MSION
bits : 8 - 8 (1 bit)
access : read-write

MSIRDY : MSIRDY
bits : 9 - 9 (1 bit)
access : read-only

HSEON : HSEON
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSERDY
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSEBYP
bits : 18 - 18 (1 bit)
access : read-write

PLLON : PLLON
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : PLLRDY
bits : 25 - 25 (1 bit)
access : read-only

CSSON : CSSON
bits : 28 - 28 (1 bit)
access : read-write

RTCPRE : RTCPRE
bits : 29 - 30 (2 bit)
access : read-write


APBRSTR

AHB peripheral reset register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBRSTR APBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOARST GPIOBRST GPIOCRST GPIODRST GPIOERST GPIOFRST CRCRST FLITFRST DMA1RST

GPIOARST : GPIOARST
bits : 0 - 0 (1 bit)
access : read-write

GPIOBRST : GPIOBRST
bits : 1 - 1 (1 bit)
access : read-write

GPIOCRST : GPIOCRST
bits : 2 - 2 (1 bit)
access : read-write

GPIODRST : GPIODRST
bits : 3 - 3 (1 bit)
access : read-write

GPIOERST : GPIOERST
bits : 4 - 4 (1 bit)
access : read-write

GPIOFRST : GPIOFRST
bits : 5 - 5 (1 bit)
access : read-write

CRCRST : CRCRST
bits : 12 - 12 (1 bit)
access : read-write

FLITFRST : FLITFRST
bits : 15 - 15 (1 bit)
access : read-write

DMA1RST : DMA1RST
bits : 24 - 24 (1 bit)
access : read-write


APB2RSTR

APB2 peripheral reset register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST TIM9RST TIM10RST TIM11RST ADC1RST SPI1RST USART1RST

SYSCFGRST : SYSCFGRST
bits : 0 - 0 (1 bit)

TIM9RST : TIM9RST
bits : 2 - 2 (1 bit)

TIM10RST : TIM10RST
bits : 3 - 3 (1 bit)

TIM11RST : TIM11RST
bits : 4 - 4 (1 bit)

ADC1RST : ADC1RST
bits : 9 - 9 (1 bit)

SPI1RST : SPI1RST
bits : 12 - 12 (1 bit)

USART1RST : USART1RST
bits : 14 - 14 (1 bit)


APB1RSTR

APB1 peripheral reset register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM4RST TIM6RST TIM7RST LCDRST WWDGRST SPI2RST USART2RST USART3RST I2C1RST I2C2RST USBRST PWRRST DACRST COMPRST

TIM2RST : TIM2RST
bits : 0 - 0 (1 bit)

TIM3RST : TIM3RST
bits : 1 - 1 (1 bit)

TIM4RST : TIM4RST
bits : 2 - 2 (1 bit)

TIM6RST : TIM6RST
bits : 4 - 4 (1 bit)

TIM7RST : TIM7RST
bits : 5 - 5 (1 bit)

LCDRST : LCDRST
bits : 9 - 9 (1 bit)

WWDGRST : WWDGRST
bits : 11 - 11 (1 bit)

SPI2RST : SPI2RST
bits : 14 - 14 (1 bit)

USART2RST : USART2RST
bits : 17 - 17 (1 bit)

USART3RST : USART3RST
bits : 18 - 18 (1 bit)

I2C1RST : I2C1RST
bits : 21 - 21 (1 bit)

I2C2RST : I2C2RST
bits : 22 - 22 (1 bit)

USBRST : USBRST
bits : 23 - 23 (1 bit)

PWRRST : PWRRST
bits : 28 - 28 (1 bit)

DACRST : DACRST
bits : 29 - 29 (1 bit)

COMPRST : COMPRST
bits : 31 - 31 (1 bit)


AHBENR

AHB peripheral clock enable register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIODEN GPIOEEN GPIOFEN CRCEN FLITFEN DMA1EN

GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)

GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)

GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)

GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)

GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)

GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)

CRCEN : CRCEN
bits : 12 - 12 (1 bit)

FLITFEN : FLITFEN
bits : 15 - 15 (1 bit)

DMA1EN : DMA1EN
bits : 24 - 24 (1 bit)


APB2ENR

APB2 peripheral clock enable register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN TIM9EN TIM10EN TIM11EN ADC1EN SPI1EN USART1EN

SYSCFGEN : SYSCFGEN
bits : 0 - 0 (1 bit)

TIM9EN : TIM9EN
bits : 2 - 2 (1 bit)

TIM10EN : TIM10EN
bits : 3 - 3 (1 bit)

TIM11EN : TIM11EN
bits : 4 - 4 (1 bit)

ADC1EN : ADC1EN
bits : 9 - 9 (1 bit)

SPI1EN : SPI1EN
bits : 12 - 12 (1 bit)

USART1EN : USART1EN
bits : 14 - 14 (1 bit)


APB1ENR

APB1 peripheral clock enable register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM4EN TIM6EN TIM7EN LCDEN WWDGEN SPI2EN USART2EN USART3EN I2C1EN I2C2EN USBEN PWREN DACEN COMPEN

TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)

TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)

TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)

TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)

TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)

LCDEN : LCDEN
bits : 9 - 9 (1 bit)

WWDGEN : WWDGEN
bits : 11 - 11 (1 bit)

SPI2EN : SPI2EN
bits : 14 - 14 (1 bit)

USART2EN : USART2EN
bits : 17 - 17 (1 bit)

USART3EN : USART3EN
bits : 18 - 18 (1 bit)

I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)

I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)

USBEN : USBEN
bits : 23 - 23 (1 bit)

PWREN : PWREN
bits : 28 - 28 (1 bit)

DACEN : DACEN
bits : 29 - 29 (1 bit)

COMPEN : COMPEN
bits : 31 - 31 (1 bit)


AHBLPENR

AHB peripheral clock enable in low power mode register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBLPENR AHBLPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOALPEN GPIOBLPEN GPIOCLPEN GPIODLPEN GPIOELPEN GPIOFLPEN CRCLPEN FLITFLPEN SRAMLPEN DMA1LPEN

GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)

GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)

GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)

GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)

GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)

GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)

CRCLPEN : CRCLPEN
bits : 12 - 12 (1 bit)

FLITFLPEN : FLITFLPEN
bits : 15 - 15 (1 bit)

SRAMLPEN : SRAMLPEN
bits : 16 - 16 (1 bit)

DMA1LPEN : DMA1LPEN
bits : 24 - 24 (1 bit)


AHB2LPENR

APB2 peripheral clock enable in low power mode register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2LPENR AHB2LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN TIM9EN TIM10EN TIM11EN ADC1EN SPI1EN USART1EN

SYSCFGEN : SYSCFGEN
bits : 0 - 0 (1 bit)

TIM9EN : TIM9EN
bits : 2 - 2 (1 bit)

TIM10EN : TIM10EN
bits : 3 - 3 (1 bit)

TIM11EN : TIM11EN
bits : 4 - 4 (1 bit)

ADC1EN : ADC1EN
bits : 9 - 9 (1 bit)

SPI1EN : SPI1EN
bits : 12 - 12 (1 bit)

USART1EN : USART1EN
bits : 14 - 14 (1 bit)


AHB1LPENR

APB1 peripheral clock enable in low power mode register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1LPENR AHB1LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2LPEN TIM3LPEN TIM4LPEN TIM6LPEN TIM7LPEN LCDLPEN WWDLPEN SPI2LPEN USART2LPEN USART3LPEN I2C1LPEN I2C2LPEN USBLPEN PWRLPEN DACLPEN COMPLPEN

TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)

TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)

TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)

TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)

TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)

LCDLPEN : LCDLPEN
bits : 9 - 9 (1 bit)

WWDLPEN : WWDLPEN
bits : 11 - 11 (1 bit)

SPI2LPEN : SPI2LPEN
bits : 14 - 14 (1 bit)

USART2LPEN : USART2LPEN
bits : 17 - 17 (1 bit)

USART3LPEN : USART3LPEN
bits : 18 - 18 (1 bit)

I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)

I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)

USBLPEN : USBLPEN
bits : 23 - 23 (1 bit)

PWRLPEN : PWRLPEN
bits : 28 - 28 (1 bit)

DACLPEN : DACLPEN
bits : 29 - 29 (1 bit)

COMPLPEN : COMPLPEN
bits : 31 - 31 (1 bit)


CSR

Control/status register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY LSEON LSERDY LSEBYP RTCSEL RTCEN RTCRST RMVF OBLRSTF PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : LSION
bits : 0 - 0 (1 bit)

LSIRDY : LSIRDY
bits : 1 - 1 (1 bit)

LSEON : LSEON
bits : 8 - 8 (1 bit)

LSERDY : LSERDY
bits : 9 - 9 (1 bit)

LSEBYP : LSEBYP
bits : 10 - 10 (1 bit)

RTCSEL : RTCSEL
bits : 16 - 17 (2 bit)

RTCEN : RTCEN
bits : 22 - 22 (1 bit)

RTCRST : RTCRST
bits : 23 - 23 (1 bit)

RMVF : RMVF
bits : 24 - 24 (1 bit)

OBLRSTF : OBLRSTF
bits : 25 - 25 (1 bit)

PINRSTF : PINRSTF
bits : 26 - 26 (1 bit)

PORRSTF : PORRSTF
bits : 27 - 27 (1 bit)

SFTRSTF : SFTRSTF
bits : 28 - 28 (1 bit)

IWDGRSTF : IWDGRSTF
bits : 29 - 29 (1 bit)

WWDGRSTF : WWDGRSTF
bits : 30 - 30 (1 bit)

LPWRRSTF : LPWRRSTF
bits : 31 - 31 (1 bit)


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSICAL HSITRIM MSIRANGE MSICAL MSITRIM

HSICAL : HSICAL
bits : 0 - 7 (8 bit)
access : read-only

HSITRIM : HSITRIM
bits : 8 - 12 (5 bit)
access : read-write

MSIRANGE : MSIRANGE
bits : 13 - 15 (3 bit)
access : read-write

MSICAL : MSICAL
bits : 16 - 23 (8 bit)
access : read-only

MSITRIM : MSITRIM
bits : 24 - 31 (8 bit)
access : read-write


CFGR

Clock configuration register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 PLLSRC PLLMUL PLLDIV MCOSEL MCOPRE

SW : SW
bits : 0 - 1 (2 bit)
access : read-write

SWS : SWS
bits : 2 - 3 (2 bit)
access : read-only

HPRE : HPRE
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : PPRE1
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : PPRE2
bits : 11 - 13 (3 bit)
access : read-write

PLLSRC : PLLSRC
bits : 16 - 16 (1 bit)
access : read-write

PLLMUL : PLLMUL
bits : 18 - 21 (4 bit)
access : read-write

PLLDIV : PLLDIV
bits : 22 - 23 (2 bit)
access : read-write

MCOSEL : MCOSEL
bits : 24 - 26 (3 bit)
access : read-write

MCOPRE : MCOPRE
bits : 28 - 30 (3 bit)
access : read-write


CIR

Clock interrupt register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR CIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF MSIRDYF CSSF LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE MSIRDYIE LSIRDYC LSERDYC HSIRDYC HSERDYC PLLRDYC MSIRDYC CSSC

LSIRDYF : LSIRDYF
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSERDYF
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSIRDYF
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSERDYF
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : PLLRDYF
bits : 4 - 4 (1 bit)
access : read-only

MSIRDYF : MSIRDYF
bits : 5 - 5 (1 bit)
access : read-only

CSSF : CSSF
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSIRDYIE
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSERDYIE
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSIRDYIE
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSERDYIE
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : PLLRDYIE
bits : 12 - 12 (1 bit)
access : read-write

MSIRDYIE : MSIRDYIE
bits : 13 - 13 (1 bit)
access : read-write

LSIRDYC : LSIRDYC
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSERDYC
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSIRDYC
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSERDYC
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : PLLRDYC
bits : 20 - 20 (1 bit)
access : write-only

MSIRDYC : MSIRDYC
bits : 21 - 21 (1 bit)
access : write-only

CSSC : CSSC
bits : 23 - 23 (1 bit)
access : write-only



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