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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SR

CR2

CR3

GTPR

DR

BRR

CR1


SR

Status register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE FE NE ORE IDLE RXNE TC TXE LBD CTS

PE : PE
bits : 0 - 0 (1 bit)
access : read-only

FE : FE
bits : 1 - 1 (1 bit)
access : read-only

NE : NE
bits : 2 - 2 (1 bit)
access : read-only

ORE : ORE
bits : 3 - 3 (1 bit)
access : read-only

IDLE : IDLE
bits : 4 - 4 (1 bit)
access : read-only

RXNE : RXNE
bits : 5 - 5 (1 bit)
access : write-only

TC : TC
bits : 6 - 6 (1 bit)
access : write-only

TXE : TXE
bits : 7 - 7 (1 bit)
access : read-only

LBD : LBD
bits : 8 - 8 (1 bit)
access : write-only

CTS : CTS
bits : 9 - 9 (1 bit)
access : write-only


CR2

Control register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD LBDL LBDIE LBCL CPHA CPOL CLKEN STOP LINEN

ADD : ADD
bits : 0 - 3 (4 bit)

LBDL : LBDL
bits : 5 - 5 (1 bit)

LBDIE : LBDIE
bits : 6 - 6 (1 bit)

LBCL : LBCL
bits : 8 - 8 (1 bit)

CPHA : CPHA
bits : 9 - 9 (1 bit)

CPOL : CPOL
bits : 10 - 10 (1 bit)

CLKEN : CLKEN
bits : 11 - 11 (1 bit)

STOP : STOP
bits : 12 - 13 (2 bit)

LINEN : LINEN
bits : 14 - 14 (1 bit)


CR3

Control register 3
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIE IREN IRLP HDSEL NACK SCEN DMAR DMAT RTSE CTSE CTSIE ONEBITE

EIE : EIE
bits : 0 - 0 (1 bit)

IREN : IREN
bits : 1 - 1 (1 bit)

IRLP : IRLP
bits : 2 - 2 (1 bit)

HDSEL : HDSEL
bits : 3 - 3 (1 bit)

NACK : NACK
bits : 4 - 4 (1 bit)

SCEN : SCEN
bits : 5 - 5 (1 bit)

DMAR : DMAR
bits : 6 - 6 (1 bit)

DMAT : DMAT
bits : 7 - 7 (1 bit)

RTSE : RTSE
bits : 8 - 8 (1 bit)

CTSE : CTSE
bits : 9 - 9 (1 bit)

CTSIE : CTSIE
bits : 10 - 10 (1 bit)

ONEBITE : ONEBITE
bits : 11 - 11 (1 bit)


GTPR

Guard time and prescaler register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTPR GTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC GT

PSC : PSC
bits : 0 - 7 (8 bit)

GT : GT
bits : 8 - 15 (8 bit)


DR

Data register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : DR
bits : 0 - 8 (9 bit)


BRR

Baud rate register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_Fraction DIV_Mantissa

DIV_Fraction : DIV_Fraction
bits : 0 - 3 (4 bit)

DIV_Mantissa : DIV_Mantissa
bits : 4 - 15 (12 bit)


CR1

Control register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBK RWU RE TE IDLEIE RXNEIE TCIE TXEIE PEIE PS PCE WAKE M UE OVER8

SBK : SBK
bits : 0 - 0 (1 bit)

RWU : RWU
bits : 1 - 1 (1 bit)

RE : RE
bits : 2 - 2 (1 bit)

TE : TE
bits : 3 - 3 (1 bit)

IDLEIE : IDLEIE
bits : 4 - 4 (1 bit)

RXNEIE : RXNEIE
bits : 5 - 5 (1 bit)

TCIE : TCIE
bits : 6 - 6 (1 bit)

TXEIE : TXEIE
bits : 7 - 7 (1 bit)

PEIE : PEIE
bits : 8 - 8 (1 bit)

PS : PS
bits : 9 - 9 (1 bit)

PCE : PCE
bits : 10 - 10 (1 bit)

WAKE : WAKE
bits : 11 - 11 (1 bit)

M : M
bits : 12 - 12 (1 bit)

UE : UE
bits : 13 - 13 (1 bit)

OVER8 : OVER8
bits : 15 - 15 (1 bit)



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