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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SR

CSR

SMPR2

SMPR3

JOFR1

JOFR2

JOFR3

JOFR4

HTR

LTR

SQR1

SQR2

SQR3

SQR4

CR1

CCR

SQR5

JSQR

JDR1

JDR2

JDR3

JDR4

DR

CR2

SMPR1


SR

ADC status register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD EOC JEOC JSTRT STRT OVR ADONS RCNR JCNR

AWD : AWD
bits : 0 - 0 (1 bit)
access : write-only

EOC : EOC
bits : 1 - 1 (1 bit)
access : write-only

JEOC : JEOC
bits : 2 - 2 (1 bit)
access : write-only

JSTRT : JSTRT
bits : 3 - 3 (1 bit)
access : write-only

STRT : STRT
bits : 4 - 4 (1 bit)
access : write-only

OVR : OVR
bits : 5 - 5 (1 bit)
access : write-only

ADONS : ADONS
bits : 6 - 6 (1 bit)
access : read-only

RCNR : RCNR
bits : 8 - 8 (1 bit)
access : read-only

JCNR : JCNR
bits : 9 - 9 (1 bit)
access : read-only


CSR

ADC common status register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD1 EOC1 JEOC1 JSTRT1 STRT1 OVR1 ADONS1

AWD1 : AWD1
bits : 0 - 0 (1 bit)

EOC1 : EOC1
bits : 1 - 1 (1 bit)

JEOC1 : JEOC1
bits : 2 - 2 (1 bit)

JSTRT1 : JSTRT1
bits : 3 - 3 (1 bit)

STRT1 : STRT1
bits : 4 - 4 (1 bit)

OVR1 : OVR1
bits : 5 - 5 (1 bit)

ADONS1 : ADONS1
bits : 6 - 6 (1 bit)


SMPR2

ADC sample time register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR2 SMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP10 SMP11 SMP12 SMP13 SMP14 SMP15 SMP16 SMP17 SMP18 SMP19

SMP10 : SMP10
bits : 0 - 2 (3 bit)

SMP11 : SMP11
bits : 3 - 5 (3 bit)

SMP12 : SMP12
bits : 6 - 8 (3 bit)

SMP13 : SMP13
bits : 9 - 11 (3 bit)

SMP14 : SMP14
bits : 12 - 14 (3 bit)

SMP15 : SMP15
bits : 15 - 17 (3 bit)

SMP16 : SMP16
bits : 18 - 20 (3 bit)

SMP17 : SMP17
bits : 21 - 23 (3 bit)

SMP18 : SMP18
bits : 24 - 26 (3 bit)

SMP19 : SMP19
bits : 27 - 29 (3 bit)


SMPR3

ADC sample time register 3
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR3 SMPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP0 SMP1 SMP2 SMP3 SMP4 SMP5 SMP6 SMP7 SMP8 SMP9

SMP0 : SMP0
bits : 0 - 2 (3 bit)

SMP1 : SMP1
bits : 3 - 5 (3 bit)

SMP2 : SMP2
bits : 6 - 8 (3 bit)

SMP3 : SMP3
bits : 9 - 11 (3 bit)

SMP4 : SMP4
bits : 12 - 14 (3 bit)

SMP5 : SMP5
bits : 15 - 17 (3 bit)

SMP6 : SMP6
bits : 18 - 20 (3 bit)

SMP7 : SMP7
bits : 21 - 23 (3 bit)

SMP8 : SMP8
bits : 24 - 26 (3 bit)

SMP9 : SMP9
bits : 27 - 29 (3 bit)


JOFR1

ADC injected channel data offset register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR1 JOFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET

JOFFSET : JOFFSET
bits : 0 - 11 (12 bit)


JOFR2

ADC injected channel data offset register 2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR2 JOFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET

JOFFSET : JOFFSET
bits : 0 - 11 (12 bit)


JOFR3

ADC injected channel data offset register 3
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR3 JOFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET

JOFFSET : JOFFSET
bits : 0 - 11 (12 bit)


JOFR4

ADC injected channel data offset register 4
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR4 JOFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET

JOFFSET : JOFFSET
bits : 0 - 11 (12 bit)


HTR

ADC watchdog higher threshold register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HTR HTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HT

HT : HT
bits : 0 - 11 (12 bit)


LTR

ADC watchdog lower threshold register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTR LTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT

LT : LT
bits : 0 - 11 (12 bit)


SQR1

ADC regular sequence register 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR1 SQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ25 SQ26 SQ27 L

SQ25 : SQ25
bits : 0 - 4 (5 bit)

SQ26 : SQ26
bits : 5 - 9 (5 bit)

SQ27 : SQ27
bits : 10 - 14 (5 bit)

L : L
bits : 20 - 24 (5 bit)


SQR2

ADC regular sequence register 2
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR2 SQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ19 SQ20 SQ21 SQ22 SQ23 SQ24

SQ19 : SQ19
bits : 0 - 4 (5 bit)

SQ20 : SQ20
bits : 5 - 9 (5 bit)

SQ21 : SQ21
bits : 10 - 14 (5 bit)

SQ22 : SQ22
bits : 15 - 19 (5 bit)

SQ23 : SQ23
bits : 20 - 24 (5 bit)

SQ24 : SQ24
bits : 25 - 29 (5 bit)


SQR3

ADC regular sequence register 3
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR3 SQR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ13 SQ14 SQ15 SQ16 SQ17 SQ18

SQ13 : SQ13
bits : 0 - 4 (5 bit)

SQ14 : SQ14
bits : 5 - 9 (5 bit)

SQ15 : SQ15
bits : 10 - 14 (5 bit)

SQ16 : SQ16
bits : 15 - 19 (5 bit)

SQ17 : SQ17
bits : 20 - 24 (5 bit)

SQ18 : SQ18
bits : 25 - 29 (5 bit)


SQR4

ADC regular sequence register 4
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR4 SQR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ7 SQ8 SQ9 SQ10 SQ11 SQ12

SQ7 : SQ7
bits : 0 - 4 (5 bit)

SQ8 : SQ8
bits : 5 - 9 (5 bit)

SQ9 : SQ9
bits : 10 - 14 (5 bit)

SQ10 : SQ10
bits : 15 - 19 (5 bit)

SQ11 : SQ11
bits : 20 - 24 (5 bit)

SQ12 : SQ12
bits : 25 - 29 (5 bit)


CR1

ADC control register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDCH EOCIE AWDIE JEOCIE SCAN AWDSGL JAUTO DISCEN JDISCEN DISCNUM PDD PDI JAWDEN AWDEN RES OVRIE

AWDCH : AWDCH
bits : 0 - 4 (5 bit)

EOCIE : EOCIE
bits : 5 - 5 (1 bit)

AWDIE : AWDIE
bits : 6 - 6 (1 bit)

JEOCIE : JEOCIE
bits : 7 - 7 (1 bit)

SCAN : SCAN
bits : 8 - 8 (1 bit)

AWDSGL : AWDSGL
bits : 9 - 9 (1 bit)

JAUTO : JAUTO
bits : 10 - 10 (1 bit)

DISCEN : DISCEN
bits : 11 - 11 (1 bit)

JDISCEN : JDISCEN
bits : 12 - 12 (1 bit)

DISCNUM : DISCNUM
bits : 13 - 15 (3 bit)

PDD : PDD
bits : 16 - 16 (1 bit)

PDI : PDI
bits : 17 - 17 (1 bit)

JAWDEN : JAWDEN
bits : 22 - 22 (1 bit)

AWDEN : AWDEN
bits : 23 - 23 (1 bit)

RES : RES
bits : 24 - 25 (2 bit)

OVRIE : OVRIE
bits : 26 - 26 (1 bit)


CCR

ADC common control register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : CR1
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCPRE TSVREFE

ADCPRE : ADCPRE
bits : 16 - 17 (2 bit)

TSVREFE : TSVREFE
bits : 23 - 23 (1 bit)


SQR5

ADC regular sequence register 5
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR5 SQR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4 SQ5 SQ6

SQ1 : SQ1
bits : 0 - 4 (5 bit)

SQ2 : SQ2
bits : 5 - 9 (5 bit)

SQ3 : SQ3
bits : 10 - 14 (5 bit)

SQ4 : SQ4
bits : 15 - 19 (5 bit)

SQ5 : SQ5
bits : 20 - 24 (5 bit)

SQ6 : SQ6
bits : 25 - 29 (5 bit)


JSQR

ADC injected sequence register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JSQR JSQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JSQ1 JSQ2 JSQ3 JSQ4 JL

JSQ1 : JSQ1
bits : 0 - 4 (5 bit)

JSQ2 : JSQ2
bits : 5 - 9 (5 bit)

JSQ3 : JSQ3
bits : 10 - 14 (5 bit)

JSQ4 : JSQ4
bits : 15 - 19 (5 bit)

JL : JL
bits : 20 - 21 (2 bit)


JDR1

ADC injected data register 1
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR1 JDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 15 (16 bit)


JDR2

ADC injected data register 2
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR2 JDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 15 (16 bit)


JDR3

ADC injected data register 3
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR3 JDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 15 (16 bit)


JDR4

ADC injected data register 4
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR4 JDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 15 (16 bit)


DR

ADC regular data register
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 15 (16 bit)


CR2

ADC control register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADON CONT DELS DMA DDS EOCS ALIGN JEXTSEL JEXTEN JSWSTART EXTSEL EXTEN SWSTART

ADON : ADON
bits : 0 - 0 (1 bit)

CONT : CONT
bits : 1 - 1 (1 bit)

DELS : DELS
bits : 4 - 6 (3 bit)

DMA : DMA
bits : 8 - 8 (1 bit)

DDS : DDS
bits : 9 - 9 (1 bit)

EOCS : EOCS
bits : 10 - 10 (1 bit)

ALIGN : ALIGN
bits : 11 - 11 (1 bit)

JEXTSEL : JEXTSEL
bits : 16 - 19 (4 bit)

JEXTEN : JEXTEN
bits : 20 - 21 (2 bit)

JSWSTART : JSWSTART
bits : 22 - 22 (1 bit)

EXTSEL : EXTSEL
bits : 24 - 27 (4 bit)

EXTEN : EXTEN
bits : 28 - 29 (2 bit)

SWSTART : SWSTART
bits : 30 - 30 (1 bit)


SMPR1

ADC sample time register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR1 SMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP20 SMP21 SMP22 SMP23 SMP24 SMP25 SMP16

SMP20 : SMP20
bits : 0 - 2 (3 bit)

SMP21 : SMP21
bits : 3 - 5 (3 bit)

SMP22 : SMP22
bits : 6 - 8 (3 bit)

SMP23 : SMP23
bits : 9 - 11 (3 bit)

SMP24 : SMP24
bits : 12 - 14 (3 bit)

SMP25 : SMP25
bits : 15 - 17 (3 bit)

SMP16 : SMP16
bits : 18 - 20 (3 bit)



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