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TIM1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

SR

EGR

CCMR1

CCER

CNT

PSC

ARR

CCR1

CCR2

CR2

OR

SMCR

DIER


CR1

TIMx control register 1
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM ARPE CKD

CEN : CEN
bits : 0 - 0 (1 bit)

UDIS : UDIS
bits : 1 - 1 (1 bit)

URS : URS
bits : 2 - 2 (1 bit)

OPM : OPM
bits : 3 - 3 (1 bit)

ARPE : ARPE
bits : 7 - 7 (1 bit)

CKD : CKD
bits : 8 - 9 (2 bit)


SR

TIMx status register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF TIF CC1OF CC2OF

UIF : UIF
bits : 0 - 0 (1 bit)

CC1IF : CC1IF
bits : 1 - 1 (1 bit)

CC2IF : CC2IF
bits : 2 - 2 (1 bit)

TIF : TIF
bits : 6 - 6 (1 bit)

CC1OF : CC1OF
bits : 9 - 9 (1 bit)

CC2OF : CC2OF
bits : 10 - 10 (1 bit)


EGR

TIMx event generation register
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EGR EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G TG

UG : UG
bits : 0 - 0 (1 bit)

CC1G : CC1G
bits : 1 - 1 (1 bit)

CC2G : CC2G
bits : 2 - 2 (1 bit)

TG : TG
bits : 6 - 6 (1 bit)


CCMR1

TIMx capture/compare mode register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMR1 CCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC1S IC1PSC IC1F IC2S IC2PSC IC2F

IC1S : IC1S
bits : 0 - 1 (2 bit)

IC1PSC : IC1PSC
bits : 2 - 3 (2 bit)

IC1F : IC1F
bits : 4 - 7 (4 bit)

IC2S : IC2S
bits : 8 - 9 (2 bit)

IC2PSC : IC2PSC
bits : 10 - 11 (2 bit)

IC2F : IC2F
bits : 12 - 15 (4 bit)


CCER

TIMx capture/compare enable register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCER CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NP CC2E CC2P CC2NP

CC1E : CC1E
bits : 0 - 0 (1 bit)

CC1P : CC1P
bits : 1 - 1 (1 bit)

CC1NP : CC1NP
bits : 3 - 3 (1 bit)

CC2E : CC2E
bits : 4 - 4 (1 bit)

CC2P : CC2P
bits : 5 - 5 (1 bit)

CC2NP : CC2NP
bits : 7 - 7 (1 bit)


CNT

TIMx counter
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 15 (16 bit)


PSC

TIMx prescaler
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 15 (16 bit)


ARR

TIMx auto-reload register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)


CCR1

TIMx capture/compare register 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : CCR1
bits : 0 - 15 (16 bit)


CCR2

TIMx capture/compare register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : CCR2
bits : 0 - 15 (16 bit)


CR2

TIMx control register 2
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMS

MMS : MMS
bits : 4 - 6 (3 bit)
access : read-only


OR

option register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OR OR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI1_RMP

TI1_RMP : TI1_RMP
bits : 0 - 1 (2 bit)
access : read-write


SMCR

TIMx slave mode control register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCR SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM ETF ETPS ECE ETP

SMS : SMS
bits : 0 - 2 (3 bit)

TS : TS
bits : 4 - 6 (3 bit)

MSM : MSM
bits : 7 - 7 (1 bit)

ETF : ETF
bits : 8 - 11 (4 bit)

ETPS : ETPS
bits : 12 - 13 (2 bit)

ECE : ECE
bits : 14 - 14 (1 bit)

ETP : ETP
bits : 15 - 15 (1 bit)


DIER

TIMx Interrupt enable register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIER DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE TIE

UIE : UIE
bits : 0 - 0 (1 bit)

CC1IE : CC1IE
bits : 1 - 1 (1 bit)

CC2IE : CC2IE
bits : 2 - 2 (1 bit)

TIE : TIE
bits : 6 - 6 (1 bit)



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