\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
TIMx control register 1
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
UDIS : UDIS
bits : 1 - 1 (1 bit)
URS : URS
bits : 2 - 2 (1 bit)
OPM : OPM
bits : 3 - 3 (1 bit)
ARPE : ARPE
bits : 7 - 7 (1 bit)
CKD : CKD
bits : 8 - 9 (2 bit)
TIMx status register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
CC1IF : CC1IF
bits : 1 - 1 (1 bit)
CC2IF : CC2IF
bits : 2 - 2 (1 bit)
TIF : TIF
bits : 6 - 6 (1 bit)
CC1OF : CC1OF
bits : 9 - 9 (1 bit)
CC2OF : CC2OF
bits : 10 - 10 (1 bit)
TIMx event generation register
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : UG
bits : 0 - 0 (1 bit)
CC1G : CC1G
bits : 1 - 1 (1 bit)
CC2G : CC2G
bits : 2 - 2 (1 bit)
TG : TG
bits : 6 - 6 (1 bit)
TIMx capture/compare mode register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC1S : IC1S
bits : 0 - 1 (2 bit)
IC1PSC : IC1PSC
bits : 2 - 3 (2 bit)
IC1F : IC1F
bits : 4 - 7 (4 bit)
IC2S : IC2S
bits : 8 - 9 (2 bit)
IC2PSC : IC2PSC
bits : 10 - 11 (2 bit)
IC2F : IC2F
bits : 12 - 15 (4 bit)
TIMx capture/compare enable register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : CC1E
bits : 0 - 0 (1 bit)
CC1P : CC1P
bits : 1 - 1 (1 bit)
CC1NP : CC1NP
bits : 3 - 3 (1 bit)
CC2E : CC2E
bits : 4 - 4 (1 bit)
CC2P : CC2P
bits : 5 - 5 (1 bit)
CC2NP : CC2NP
bits : 7 - 7 (1 bit)
TIMx counter
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
TIMx prescaler
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC
bits : 0 - 15 (16 bit)
TIMx auto-reload register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ARR
bits : 0 - 15 (16 bit)
TIMx capture/compare register 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : CCR1
bits : 0 - 15 (16 bit)
TIMx capture/compare register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : CCR2
bits : 0 - 15 (16 bit)
TIMx control register 2
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMS : MMS
bits : 4 - 6 (3 bit)
access : read-only
option register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1_RMP : TI1_RMP
bits : 0 - 1 (2 bit)
access : read-write
TIMx slave mode control register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : SMS
bits : 0 - 2 (3 bit)
TS : TS
bits : 4 - 6 (3 bit)
MSM : MSM
bits : 7 - 7 (1 bit)
ETF : ETF
bits : 8 - 11 (4 bit)
ETPS : ETPS
bits : 12 - 13 (2 bit)
ECE : ECE
bits : 14 - 14 (1 bit)
ETP : ETP
bits : 15 - 15 (1 bit)
TIMx Interrupt enable register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
CC1IE : CC1IE
bits : 1 - 1 (1 bit)
CC2IE : CC2IE
bits : 2 - 2 (1 bit)
TIE : TIE
bits : 6 - 6 (1 bit)
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