\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
PWR power control register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPDS : LPDS
bits : 0 - 0 (1 bit)
access : read-write
PDDS : PDDS
bits : 1 - 1 (1 bit)
access : read-write
CWUF : CWUF
bits : 2 - 2 (1 bit)
access : write-only
CSBF : CSBF
bits : 3 - 3 (1 bit)
access : write-only
PVDE : PVDE
bits : 4 - 4 (1 bit)
access : read-write
PLS : PLS
bits : 5 - 7 (3 bit)
access : read-write
DBP : DBP
bits : 8 - 8 (1 bit)
access : read-write
ULP : ULP
bits : 9 - 9 (1 bit)
access : read-write
FWU : FWU
bits : 10 - 10 (1 bit)
access : read-write
VOS : VOS
bits : 11 - 12 (2 bit)
access : read-write
LPRUN : LPRUN
bits : 14 - 14 (1 bit)
access : read-write
PWR power control/status register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUF : WUF
bits : 0 - 0 (1 bit)
access : read-only
SBF : SBF
bits : 1 - 1 (1 bit)
access : read-only
PVDO : PVDO
bits : 2 - 2 (1 bit)
access : read-only
VREFINTRDYF : VREFINTRDYF
bits : 3 - 3 (1 bit)
access : read-only
VOSF : VOSF
bits : 4 - 4 (1 bit)
access : read-only
EWUP1 : EWUP1
bits : 8 - 8 (1 bit)
access : read-write
EWUP2 : EWUP2
bits : 9 - 9 (1 bit)
access : read-write
EWUP3 : EWUP3
bits : 10 - 10 (1 bit)
access : read-write
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