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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CSR


CR

PWR power control register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPDS PDDS CWUF CSBF PVDE PLS DBP ULP FWU VOS LPRUN

LPDS : LPDS
bits : 0 - 0 (1 bit)
access : read-write

PDDS : PDDS
bits : 1 - 1 (1 bit)
access : read-write

CWUF : CWUF
bits : 2 - 2 (1 bit)
access : write-only

CSBF : CSBF
bits : 3 - 3 (1 bit)
access : write-only

PVDE : PVDE
bits : 4 - 4 (1 bit)
access : read-write

PLS : PLS
bits : 5 - 7 (3 bit)
access : read-write

DBP : DBP
bits : 8 - 8 (1 bit)
access : read-write

ULP : ULP
bits : 9 - 9 (1 bit)
access : read-write

FWU : FWU
bits : 10 - 10 (1 bit)
access : read-write

VOS : VOS
bits : 11 - 12 (2 bit)
access : read-write

LPRUN : LPRUN
bits : 14 - 14 (1 bit)
access : read-write


CSR

PWR power control/status register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUF SBF PVDO VREFINTRDYF VOSF EWUP1 EWUP2 EWUP3

WUF : WUF
bits : 0 - 0 (1 bit)
access : read-only

SBF : SBF
bits : 1 - 1 (1 bit)
access : read-only

PVDO : PVDO
bits : 2 - 2 (1 bit)
access : read-only

VREFINTRDYF : VREFINTRDYF
bits : 3 - 3 (1 bit)
access : read-only

VOSF : VOSF
bits : 4 - 4 (1 bit)
access : read-only

EWUP1 : EWUP1
bits : 8 - 8 (1 bit)
access : read-write

EWUP2 : EWUP2
bits : 9 - 9 (1 bit)
access : read-write

EWUP3 : EWUP3
bits : 10 - 10 (1 bit)
access : read-write



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