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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

DR

SR1

SR2

CCR

TRISE

CR2

OAR1

OAR2


CR1

Control register 1
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE SMBUS SMBTYPE ENARP ENPEC ENGC NOSTRETCH START STOP ACK POS PEC ALERT SWRST

PE : PE
bits : 0 - 0 (1 bit)

SMBUS : SMBUS
bits : 1 - 1 (1 bit)

SMBTYPE : SMBTYPE
bits : 3 - 3 (1 bit)

ENARP : ENARP
bits : 4 - 4 (1 bit)

ENPEC : ENPEC
bits : 5 - 5 (1 bit)

ENGC : ENGC
bits : 6 - 6 (1 bit)

NOSTRETCH : NOSTRETCH
bits : 7 - 7 (1 bit)

START : START
bits : 8 - 8 (1 bit)

STOP : STOP
bits : 9 - 9 (1 bit)

ACK : ACK
bits : 10 - 10 (1 bit)

POS : POS
bits : 11 - 11 (1 bit)

PEC : PEC
bits : 12 - 12 (1 bit)

ALERT : ALERT
bits : 13 - 13 (1 bit)

SWRST : SWRST
bits : 15 - 15 (1 bit)


DR

Data register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : DR
bits : 0 - 7 (8 bit)


SR1

Status register 1
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SB ADDR BTF ADD10 STOPF RxNE TxE BERR ARLO AF OVR PECERR TIMEOUT SMBALERT

SB : SB
bits : 0 - 0 (1 bit)

ADDR : ADDR
bits : 1 - 1 (1 bit)

BTF : BTF
bits : 2 - 2 (1 bit)

ADD10 : ADD10
bits : 3 - 3 (1 bit)

STOPF : STOPF
bits : 4 - 4 (1 bit)

RxNE : RxNE
bits : 6 - 6 (1 bit)

TxE : TxE
bits : 7 - 7 (1 bit)

BERR : BERR
bits : 8 - 8 (1 bit)

ARLO : ARLO
bits : 9 - 9 (1 bit)

AF : AF
bits : 10 - 10 (1 bit)

OVR : OVR
bits : 11 - 11 (1 bit)

PECERR : PECERR
bits : 12 - 12 (1 bit)

TIMEOUT : TIMEOUT
bits : 14 - 14 (1 bit)

SMBALERT : SMBALERT
bits : 15 - 15 (1 bit)


SR2

Status register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSL BUSY TRA GENCALL SMBDEFAULT SMBHOST DUALF PEC

MSL : MSL
bits : 0 - 0 (1 bit)

BUSY : BUSY
bits : 1 - 1 (1 bit)

TRA : TRA
bits : 2 - 2 (1 bit)

GENCALL : GENCALL
bits : 4 - 4 (1 bit)

SMBDEFAULT : SMBDEFAULT
bits : 5 - 5 (1 bit)

SMBHOST : SMBHOST
bits : 6 - 6 (1 bit)

DUALF : DUALF
bits : 7 - 7 (1 bit)

PEC : PEC
bits : 8 - 15 (8 bit)


CCR

Clock control register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR DUTY F_S

CCR : CCR
bits : 0 - 11 (12 bit)

DUTY : DUTY
bits : 14 - 14 (1 bit)

F_S : F_S
bits : 15 - 15 (1 bit)


TRISE

TRISE register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRISE TRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRISE

TRISE : TRISE
bits : 0 - 5 (6 bit)


CR2

Control register 2
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ ITERREN ITEVTEN ITBUFEN DMAEN LAST

FREQ : FREQ
bits : 0 - 5 (6 bit)

ITERREN : ITERREN
bits : 8 - 8 (1 bit)

ITEVTEN : ITEVTEN
bits : 9 - 9 (1 bit)

ITBUFEN : ITBUFEN
bits : 10 - 10 (1 bit)

DMAEN : DMAEN
bits : 11 - 11 (1 bit)

LAST : LAST
bits : 12 - 12 (1 bit)


OAR1

Own address register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OAR1 OAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD0 ADD ADDMODE

ADD0 : ADD0
bits : 0 - 0 (1 bit)

ADD : ADD
bits : 1 - 9 (9 bit)

ADDMODE : ADDMODE
bits : 15 - 15 (1 bit)


OAR2

Own address register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OAR2 OAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDUAL ADD2

ENDUAL : ENDUAL
bits : 0 - 0 (1 bit)

ADD2 : ADD2
bits : 1 - 7 (7 bit)



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