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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt mask register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : Event mask on line 0
bits : 0 - 0 (1 bit)
MR1 : Event mask on line 1
bits : 1 - 1 (1 bit)
MR2 : Event mask on line 2
bits : 2 - 2 (1 bit)
MR3 : Event mask on line 3
bits : 3 - 3 (1 bit)
MR4 : Event mask on line 4
bits : 4 - 4 (1 bit)
MR5 : Event mask on line 5
bits : 5 - 5 (1 bit)
MR6 : Event mask on line 6
bits : 6 - 6 (1 bit)
MR7 : Event mask on line 7
bits : 7 - 7 (1 bit)
MR8 : Event mask on line 8
bits : 8 - 8 (1 bit)
MR9 : Event mask on line 9
bits : 9 - 9 (1 bit)
MR10 : Event mask on line 10
bits : 10 - 10 (1 bit)
MR11 : Event mask on line 11
bits : 11 - 11 (1 bit)
MR12 : Event mask on line 12
bits : 12 - 12 (1 bit)
MR13 : Event mask on line 13
bits : 13 - 13 (1 bit)
MR14 : Event mask on line 14
bits : 14 - 14 (1 bit)
MR15 : Event mask on line 15
bits : 15 - 15 (1 bit)
MR16 : Event mask on line 16
bits : 16 - 16 (1 bit)
MR17 : Event mask on line 17
bits : 17 - 17 (1 bit)
MR18 : Event mask on line 18
bits : 18 - 18 (1 bit)
MR19 : Event mask on line 19
bits : 19 - 19 (1 bit)
MR20 : Event mask on line 20
bits : 20 - 20 (1 bit)
MR21 : Event mask on line 21
bits : 21 - 21 (1 bit)
MR22 : Event mask on line 22
bits : 22 - 22 (1 bit)
Software interrupt event register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIER0 : Software Interrupt on line x
bits : 0 - 0 (1 bit)
SWIER1 : Software Interrupt on line x
bits : 1 - 1 (1 bit)
SWIER2 : Software Interrupt on line x
bits : 2 - 2 (1 bit)
SWIER3 : Software Interrupt on line x
bits : 3 - 3 (1 bit)
SWIER4 : Software Interrupt on line x
bits : 4 - 4 (1 bit)
SWIER5 : Software Interrupt on line x
bits : 5 - 5 (1 bit)
SWIER6 : Software Interrupt on line x
bits : 6 - 6 (1 bit)
SWIER7 : Software Interrupt on line x
bits : 7 - 7 (1 bit)
SWIER8 : Software Interrupt on line x
bits : 8 - 8 (1 bit)
SWIER9 : Software Interrupt on line x
bits : 9 - 9 (1 bit)
SWIER10 : Software Interrupt on line x
bits : 10 - 10 (1 bit)
SWIER11 : Software Interrupt on line x
bits : 11 - 11 (1 bit)
SWIER12 : Software Interrupt on line x
bits : 12 - 12 (1 bit)
SWIER13 : Software Interrupt on line x
bits : 13 - 13 (1 bit)
SWIER14 : Software Interrupt on line x
bits : 14 - 14 (1 bit)
SWIER15 : Software Interrupt on line x
bits : 15 - 15 (1 bit)
SWIER16 : Software Interrupt on line x
bits : 16 - 16 (1 bit)
SWIER17 : Software Interrupt on line x
bits : 17 - 17 (1 bit)
SWIER18 : Software Interrupt on line x
bits : 18 - 18 (1 bit)
SWIER19 : Software Interrupt on line x
bits : 19 - 19 (1 bit)
SWIER20 : Software Interrupt on line x
bits : 20 - 20 (1 bit)
SWIER22 : Software Interrupt on line x
bits : 21 - 21 (1 bit)
Pending register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR0 : Pending bit x
bits : 0 - 0 (1 bit)
PR1 : Pending bit x
bits : 1 - 1 (1 bit)
PR2 : Pending bit x
bits : 2 - 2 (1 bit)
PR3 : Pending bit x
bits : 3 - 3 (1 bit)
PR4 : Pending bit x
bits : 4 - 4 (1 bit)
PR5 : Pending bit x
bits : 5 - 5 (1 bit)
PR6 : Pending bit x
bits : 6 - 6 (1 bit)
PR7 : Pending bit x
bits : 7 - 7 (1 bit)
PR8 : Pending bit x
bits : 8 - 8 (1 bit)
PR9 : Pending bit x
bits : 9 - 9 (1 bit)
PR10 : Pending bit x
bits : 10 - 10 (1 bit)
PR11 : Pending bit x
bits : 11 - 11 (1 bit)
PR12 : Pending bit x
bits : 12 - 12 (1 bit)
PR13 : Pending bit x
bits : 13 - 13 (1 bit)
PR14 : Pending bit x
bits : 14 - 14 (1 bit)
PR15 : Pending bit x
bits : 15 - 15 (1 bit)
PR16 : Pending bit x
bits : 16 - 16 (1 bit)
PR17 : Pending bit x
bits : 17 - 17 (1 bit)
PR218 : Pending bit x
bits : 18 - 18 (1 bit)
PR19 : Pending bit x
bits : 19 - 19 (1 bit)
PR20 : Pending bit x
bits : 20 - 20 (1 bit)
PR21 : Pending bit x
bits : 21 - 21 (1 bit)
PR22 : Pending bit x
bits : 22 - 22 (1 bit)
Event mask register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : Event mask on line x
bits : 0 - 0 (1 bit)
MR1 : Event mask on line x
bits : 1 - 1 (1 bit)
MR2 : Event mask on line x
bits : 2 - 2 (1 bit)
MR3 : Event mask on line x
bits : 3 - 3 (1 bit)
MR4 : Event mask on line x
bits : 4 - 4 (1 bit)
MR5 : Event mask on line x
bits : 5 - 5 (1 bit)
MR6 : Event mask on line x
bits : 6 - 6 (1 bit)
MR7 : Event mask on line x
bits : 7 - 7 (1 bit)
MR8 : Event mask on line x
bits : 8 - 8 (1 bit)
MR9 : Event mask on line x
bits : 9 - 9 (1 bit)
MR10 : Event mask on line x
bits : 10 - 10 (1 bit)
MR11 : Event mask on line x
bits : 11 - 11 (1 bit)
MR12 : Event mask on line x
bits : 12 - 12 (1 bit)
MR13 : Event mask on line x
bits : 13 - 13 (1 bit)
MR14 : Event mask on line x
bits : 14 - 14 (1 bit)
MR15 : Event mask on line x
bits : 15 - 15 (1 bit)
MR16 : Event mask on line x
bits : 16 - 16 (1 bit)
MR17 : Event mask on line x
bits : 17 - 17 (1 bit)
MR18 : Event mask on line x
bits : 18 - 18 (1 bit)
MR19 : Event mask on line x
bits : 19 - 19 (1 bit)
MR20 : Event mask on line x
bits : 20 - 20 (1 bit)
MR21 : Event mask on line x
bits : 21 - 21 (1 bit)
MR22 : Event mask on line x
bits : 22 - 22 (1 bit)
Rising trigger selection register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR0 : Rising trigger event configuration bit of line x
bits : 0 - 0 (1 bit)
TR1 : Rising trigger event configuration bit of line x
bits : 1 - 1 (1 bit)
TR2 : Rising trigger event configuration bit of line x
bits : 2 - 2 (1 bit)
TR3 : Rising trigger event configuration bit of line x
bits : 3 - 3 (1 bit)
TR4 : Rising trigger event configuration bit of line x
bits : 4 - 4 (1 bit)
TR5 : Rising trigger event configuration bit of line x
bits : 5 - 5 (1 bit)
TR6 : Rising trigger event configuration bit of line x
bits : 6 - 6 (1 bit)
TR7 : Rising trigger event configuration bit of line x
bits : 7 - 7 (1 bit)
TR8 : Rising trigger event configuration bit of line x
bits : 8 - 8 (1 bit)
TR9 : Rising trigger event configuration bit of line x
bits : 9 - 9 (1 bit)
TR10 : Rising trigger event configuration bit of line x
bits : 10 - 10 (1 bit)
TR11 : Rising trigger event configuration bit of line x
bits : 11 - 11 (1 bit)
TR12 : Rising trigger event configuration bit of line x
bits : 12 - 12 (1 bit)
TR13 : Rising trigger event configuration bit of line x
bits : 13 - 13 (1 bit)
TR14 : Rising trigger event configuration bit of line x
bits : 14 - 14 (1 bit)
TR15 : Rising trigger event configuration bit of line x
bits : 15 - 15 (1 bit)
TR16 : Rising trigger event configuration bit of line x
bits : 16 - 16 (1 bit)
TR17 : Rising trigger event configuration bit of line x
bits : 17 - 17 (1 bit)
TR18 : Rising trigger event configuration bit of line x
bits : 18 - 18 (1 bit)
TR19 : Rising trigger event configuration bit of line x
bits : 19 - 19 (1 bit)
TR20 : Rising trigger event configuration bit of line x
bits : 20 - 20 (1 bit)
TR21 : Rising trigger event configuration bit of line x
bits : 21 - 21 (1 bit)
TR22 : Rising trigger event configuration bit of line x
bits : 22 - 22 (1 bit)
Falling trigger selection register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR0 : Falling trigger event configuration bit of line x
bits : 0 - 0 (1 bit)
TR1 : Falling trigger event configuration bit of line x
bits : 1 - 1 (1 bit)
TR2 : Falling trigger event configuration bit of line x
bits : 2 - 2 (1 bit)
TR3 : Falling trigger event configuration bit of line x
bits : 3 - 3 (1 bit)
TR4 : Falling trigger event configuration bit of line x
bits : 4 - 4 (1 bit)
TR5 : Falling trigger event configuration bit of line x
bits : 5 - 5 (1 bit)
TR6 : Falling trigger event configuration bit of line x
bits : 6 - 6 (1 bit)
TR7 : Falling trigger event configuration bit of line x
bits : 7 - 7 (1 bit)
TR8 : Falling trigger event configuration bit of line x
bits : 8 - 8 (1 bit)
TR9 : Falling trigger event configuration bit of line x
bits : 9 - 9 (1 bit)
TR10 : Falling trigger event configuration bit of line x
bits : 10 - 10 (1 bit)
TR11 : Falling trigger event configuration bit of line x
bits : 11 - 11 (1 bit)
TR12 : Falling trigger event configuration bit of line x
bits : 12 - 12 (1 bit)
TR13 : Falling trigger event configuration bit of line x
bits : 13 - 13 (1 bit)
TR14 : Falling trigger event configuration bit of line x
bits : 14 - 14 (1 bit)
TR15 : Falling trigger event configuration bit of line x
bits : 15 - 15 (1 bit)
TR16 : Falling trigger event configuration bit of line x
bits : 16 - 16 (1 bit)
TR17 : Falling trigger event configuration bit of line x
bits : 17 - 17 (1 bit)
TR18 : Falling trigger event configuration bit of line x
bits : 18 - 18 (1 bit)
TR19 : Falling trigger event configuration bit of line x
bits : 19 - 19 (1 bit)
TR20 : Falling trigger event configuration bit of line x
bits : 20 - 20 (1 bit)
TR21 : Falling trigger event configuration bit of line x
bits : 21 - 21 (1 bit)
TR22 : Falling trigger event configuration bit of line x
bits : 22 - 22 (1 bit)
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