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DDRPHYC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x298 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DDRPHYC_RIDR (RIDR)

DDRPHYC_DLLGCR (DLLGCR)

DDRPHYC_BISTRR (BISTRR)

DDRPHYC_BISTMSKR0 (BISTMSKR0)

DDRPHYC_BISTMSKR1 (BISTMSKR1)

DDRPHYC_BISTWCR (BISTWCR)

DDRPHYC_BISTLSR (BISTLSR)

DDRPHYC_BISTAR0 (BISTAR0)

DDRPHYC_BISTAR1 (BISTAR1)

DDRPHYC_BISTAR2 (BISTAR2)

DDRPHYC_BISTUDPR (BISTUDPR)

DDRPHYC_BISTGSR (BISTGSR)

DDRPHYC_BISTWER (BISTWER)

DDRPHYC_BISTBER0 (BISTBER0)

DDRPHYC_BISTBER1 (BISTBER1)

DDRPHYC_BISTBER2 (BISTBER2)

DDRPHYC_BISTWCSR (BISTWCSR)

DDRPHYC_BISTFWR0 (BISTFWR0)

DDRPHYC_ACDLLCR (ACDLLCR)

DDRPHYC_BISTFWR1 (BISTFWR1)

DDRPHYC_GPR0 (GPR0)

DDRPHYC_GPR1 (GPR1)

DDRPHYC_PTR0 (PTR0)

DDRPHYC_ZQ0CR0 (ZQ0CR0)

DDRPHYC_ZQ0CR1 (ZQ0CR1)

DDRPHYC_ZQ0SR0 (ZQ0SR0)

DDRPHYC_ZQ0SR1 (ZQ0SR1)

DDRPHYC_PTR1 (PTR1)

DDRPHYC_DX0GCR (DX0GCR)

DDRPHYC_DX0GSR0 (DX0GSR0)

DDRPHYC_DX0GSR1 (DX0GSR1)

DDRPHYC_DX0DLLCR (DX0DLLCR)

DDRPHYC_DX0DQTR (DX0DQTR)

DDRPHYC_DX0DQSTR (DX0DQSTR)

DDRPHYC_PTR2 (PTR2)

DDRPHYC_DX1GCR (DX1GCR)

DDRPHYC_DX1GSR0 (DX1GSR0)

DDRPHYC_DX1GSR1 (DX1GSR1)

DDRPHYC_DX1DLLCR (DX1DLLCR)

DDRPHYC_DX1DQTR (DX1DQTR)

DDRPHYC_DX1DQSTR (DX1DQSTR)

DDRPHYC_ACIOCR (ACIOCR)

DDRPHYC_DX2GCR (DX2GCR)

DDRPHYC_DX2GSR0 (DX2GSR0)

DDRPHYC_DX2GSR1 (DX2GSR1)

DDRPHYC_DX2DLLCR (DX2DLLCR)

DDRPHYC_DX2DQTR (DX2DQTR)

DDRPHYC_DX2DQSTR (DX2DQSTR)

DDRPHYC_DXCCR (DXCCR)

DDRPHYC_DX3GCR (DX3GCR)

DDRPHYC_DX3GSR0 (DX3GSR0)

DDRPHYC_DX3GSR1 (DX3GSR1)

DDRPHYC_DX3DLLCR (DX3DLLCR)

DDRPHYC_DX3DQTR (DX3DQTR)

DDRPHYC_DX3DQSTR (DX3DQSTR)

DDRPHYC_DSGCR (DSGCR)

DDRPHYC_DCR (DCR)

DDRPHYC_DTPR0 (DTPR0)

DDRPHYC_DTPR1 (DTPR1)

DDRPHYC_DTPR2 (DTPR2)

DDRPHYC_PIR (PIR)

DDRPHYC_MR0 (MR0)

DDRPHYC_MR1 (MR1)

DDRPHYC_MR2 (MR2)

DDRPHYC_MR3 (MR3)

DDRPHYC_ODTCR (ODTCR)

DDRPHYC_DTAR (DTAR)

DDRPHYC_DTDR0 (DTDR0)

DDRPHYC_DTDR1 (DTDR1)

DDRPHYC_PGCR (PGCR)

DDRPHYC_PGSR (PGSR)

DDRPHYC_DCUAR (DCUAR)

DDRPHYC_DCUDR (DCUDR)

DDRPHYC_DCURR (DCURR)

DDRPHYC_DCULR (DCULR)

DDRPHYC_DCUGCR (DCUGCR)

DDRPHYC_DCUTPR (DCUTPR)

DDRPHYC_DCUSR0 (DCUSR0)

DDRPHYC_DCUSR1 (DCUSR1)


DDRPHYC_RIDR (RIDR)

RIDR register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_RIDR DDRPHYC_RIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PUBMNR PUBMDR PUBMJR PHYMNR PHYMDR PHYMJR UDRID

PUBMNR : PUBMNR
bits : 0 - 3 (4 bit)
access : read-only

PUBMDR : PUBMDR
bits : 4 - 7 (4 bit)
access : read-only

PUBMJR : PUBMJR
bits : 8 - 11 (4 bit)
access : read-only

PHYMNR : PHYMNR
bits : 12 - 15 (4 bit)
access : read-only

PHYMDR : PHYMDR
bits : 16 - 19 (4 bit)
access : read-only

PHYMJR : PHYMJR
bits : 20 - 23 (4 bit)
access : read-only

UDRID : UDRID
bits : 24 - 31 (8 bit)
access : read-only


DDRPHYC_DLLGCR (DLLGCR)

DLLGCR register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DLLGCR DDRPHYC_DLLGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRES IPUMP TESTEN DTC ATC TESTSW MBIAS SBIAS2_0 BPS200 SBIAS5_3 FDTRMSL LOCKDET DLLRSVD2

DRES : DRES
bits : 0 - 1 (2 bit)
access : read-write

IPUMP : IPUMP
bits : 2 - 4 (3 bit)
access : read-write

TESTEN : TESTEN
bits : 5 - 5 (1 bit)
access : read-write

DTC : DTC
bits : 6 - 8 (3 bit)
access : read-write

ATC : ATC
bits : 9 - 10 (2 bit)
access : read-write

TESTSW : TESTSW
bits : 11 - 11 (1 bit)
access : read-write

MBIAS : MBIAS
bits : 12 - 19 (8 bit)
access : read-write

SBIAS2_0 : SBIAS2_0
bits : 20 - 22 (3 bit)
access : read-write

BPS200 : BPS200
bits : 23 - 23 (1 bit)
access : read-write

SBIAS5_3 : SBIAS5_3
bits : 24 - 26 (3 bit)
access : read-write

FDTRMSL : FDTRMSL
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Nominal delay

0x1 : B_0x1

Nominal delay less 10

0x2 : B_0x2

Nominal delay more 10

0x3 : B_0x3

Nominal delay more 20

End of enumeration elements list.

LOCKDET : LOCKDET
bits : 29 - 29 (1 bit)
access : read-write

DLLRSVD2 : DLLRSVD2
bits : 30 - 31 (2 bit)
access : read-write


DDRPHYC_BISTRR (BISTRR)

BISTRR register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTRR DDRPHYC_BISTRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINST BMODE BINF NFAIL BSCONF BDXEN BACEN BDMEN BDPAT BDXSEL BCKSEL

BINST : BINST
bits : 0 - 2 (3 bit)
access : read-write

BMODE : BMODE
bits : 3 - 3 (1 bit)
access : read-write

BINF : BINF
bits : 4 - 4 (1 bit)
access : read-write

NFAIL : NFAIL
bits : 5 - 12 (8 bit)
access : read-write

BSCONF : BSCONF
bits : 13 - 13 (1 bit)
access : read-write

BDXEN : BDXEN
bits : 14 - 14 (1 bit)
access : read-write

BACEN : BACEN
bits : 15 - 15 (1 bit)
access : read-write

BDMEN : BDMEN
bits : 16 - 16 (1 bit)
access : read-write

BDPAT : BDPAT
bits : 17 - 18 (2 bit)
access : read-write

BDXSEL : BDXSEL
bits : 19 - 22 (4 bit)
access : read-write

BCKSEL : BCKSEL
bits : 23 - 25 (3 bit)
access : read-write


DDRPHYC_BISTMSKR0 (BISTMSKR0)

BISTMSKR0 register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTMSKR0 DDRPHYC_BISTMSKR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMSK BAMSK WEMSK CKEMSK CSMSK ODTMSK

AMSK : AMSK
bits : 0 - 15 (16 bit)
access : read-write

BAMSK : BAMSK
bits : 16 - 18 (3 bit)
access : read-write

WEMSK : WEMSK
bits : 19 - 19 (1 bit)
access : read-write

CKEMSK : CKEMSK
bits : 20 - 23 (4 bit)
access : read-write

CSMSK : CSMSK
bits : 24 - 27 (4 bit)
access : read-write

ODTMSK : ODTMSK
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_BISTMSKR1 (BISTMSKR1)

BISTMSKR1 register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTMSKR1 DDRPHYC_BISTMSKR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQMSK DMMSK RASMSK CASMSK PARMSK TPDMASK

DQMSK : DQMSK
bits : 0 - 15 (16 bit)
access : read-write

DMMSK : DMMSK
bits : 16 - 17 (2 bit)
access : read-write

RASMSK : RASMSK
bits : 18 - 18 (1 bit)
access : read-write

CASMSK : CASMSK
bits : 19 - 19 (1 bit)
access : read-write

PARMSK : PARMSK
bits : 30 - 30 (1 bit)
access : read-write

TPDMASK : TPDMASK
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_BISTWCR (BISTWCR)

BISTWCR register
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTWCR DDRPHYC_BISTWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BWCNT

BWCNT : BWCNT
bits : 0 - 15 (16 bit)
access : read-write


DDRPHYC_BISTLSR (BISTLSR)

BISTLSR register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTLSR DDRPHYC_BISTLSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BISTLSR

BISTLSR : BISTLSR
bits : 0 - 31 (32 bit)
access : read-write


DDRPHYC_BISTAR0 (BISTAR0)

BISTAR0 register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTAR0 DDRPHYC_BISTAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCOL BROW BBANK

BCOL : BCOL
bits : 0 - 11 (12 bit)
access : read-write

BROW : BROW
bits : 12 - 27 (16 bit)
access : read-write

BBANK : BBANK
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_BISTAR1 (BISTAR1)

BISTAR1 register
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTAR1 DDRPHYC_BISTAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRANK BMRANK BAINC

BRANK : BRANK
bits : 0 - 1 (2 bit)
access : read-write

BMRANK : BMRANK
bits : 2 - 3 (2 bit)
access : read-write

BAINC : BAINC
bits : 4 - 15 (12 bit)
access : read-write


DDRPHYC_BISTAR2 (BISTAR2)

BISTAR2 register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTAR2 DDRPHYC_BISTAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMCOL BMROW BMBANK

BMCOL : BMCOL
bits : 0 - 11 (12 bit)
access : read-write

BMROW : BMROW
bits : 12 - 27 (16 bit)
access : read-write

BMBANK : BMBANK
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_BISTUDPR (BISTUDPR)

BISTUDPR register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTUDPR DDRPHYC_BISTUDPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUDP0 BUDP1

BUDP0 : BUDP0
bits : 0 - 15 (16 bit)
access : read-write

BUDP1 : BUDP1
bits : 16 - 31 (16 bit)
access : read-write


DDRPHYC_BISTGSR (BISTGSR)

BISTGSR register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTGSR DDRPHYC_BISTGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDONE BACERR BDXERR PARBER TPDBER DMBER RASBER CASBER

BDONE : BDONE
bits : 0 - 0 (1 bit)
access : read-only

BACERR : BACERR
bits : 1 - 1 (1 bit)
access : read-only

BDXERR : BDXERR
bits : 2 - 2 (1 bit)
access : read-only

PARBER : PARBER
bits : 20 - 21 (2 bit)
access : read-only

TPDBER : TPDBER
bits : 22 - 23 (2 bit)
access : read-only

DMBER : DMBER
bits : 24 - 27 (4 bit)
access : read-only

RASBER : RASBER
bits : 28 - 29 (2 bit)
access : read-only

CASBER : CASBER
bits : 30 - 31 (2 bit)
access : read-only


DDRPHYC_BISTWER (BISTWER)

BISTWER register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTWER DDRPHYC_BISTWER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACWER DXWER

ACWER : ACWER
bits : 0 - 15 (16 bit)
access : read-only

DXWER : DXWER
bits : 16 - 31 (16 bit)
access : read-only


DDRPHYC_BISTBER0 (BISTBER0)

BISTBER0 register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTBER0 DDRPHYC_BISTBER0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABER

ABER : ABER
bits : 0 - 31 (32 bit)
access : read-only


DDRPHYC_BISTBER1 (BISTBER1)

BISTBER1 register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTBER1 DDRPHYC_BISTBER1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BABER WEBER CKEBER CSBER ODTBER

BABER : BABER
bits : 0 - 5 (6 bit)
access : read-only

WEBER : WEBER
bits : 6 - 7 (2 bit)
access : read-only

CKEBER : CKEBER
bits : 8 - 15 (8 bit)
access : read-only

CSBER : CSBER
bits : 16 - 23 (8 bit)
access : read-only

ODTBER : ODTBER
bits : 24 - 31 (8 bit)
access : read-only


DDRPHYC_BISTBER2 (BISTBER2)

BISTBER2 register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTBER2 DDRPHYC_BISTBER2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQBER

DQBER : DQBER
bits : 0 - 31 (32 bit)
access : read-only


DDRPHYC_BISTWCSR (BISTWCSR)

BISTWCSR register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTWCSR DDRPHYC_BISTWCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACWCNT DXWCNT

ACWCNT : ACWCNT
bits : 0 - 15 (16 bit)
access : read-only

DXWCNT : DXWCNT
bits : 16 - 31 (16 bit)
access : read-only


DDRPHYC_BISTFWR0 (BISTFWR0)

BISTFWR0 register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTFWR0 DDRPHYC_BISTFWR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWEBS BAWEBS WEWEBS CKEWEBS CSWEBS ODTWEBS

AWEBS : AWEBS
bits : 0 - 15 (16 bit)
access : read-only

BAWEBS : BAWEBS
bits : 16 - 18 (3 bit)
access : read-only

WEWEBS : WEWEBS
bits : 19 - 19 (1 bit)
access : read-only

CKEWEBS : CKEWEBS
bits : 20 - 23 (4 bit)
access : read-only

CSWEBS : CSWEBS
bits : 24 - 27 (4 bit)
access : read-only

ODTWEBS : ODTWEBS
bits : 28 - 31 (4 bit)
access : read-only


DDRPHYC_ACDLLCR (ACDLLCR)

ACDLLCR register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ACDLLCR DDRPHYC_ACDLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFBDLY MFWDLY ATESTEN DLLSRST DLLDIS

MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write

MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write

ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write

DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write

DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_BISTFWR1 (BISTFWR1)

BISTFWR1 register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_BISTFWR1 DDRPHYC_BISTFWR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQWEBS DMWEBS RASWEBS CASWEBS PARWEBS TPDWEBS

DQWEBS : DQWEBS
bits : 0 - 15 (16 bit)
access : read-only

DMWEBS : DMWEBS
bits : 16 - 17 (2 bit)
access : read-only

RASWEBS : RASWEBS
bits : 18 - 18 (1 bit)
access : read-only

CASWEBS : CASWEBS
bits : 19 - 19 (1 bit)
access : read-only

PARWEBS : PARWEBS
bits : 30 - 30 (1 bit)
access : read-only

TPDWEBS : TPDWEBS
bits : 31 - 31 (1 bit)
access : read-only


DDRPHYC_GPR0 (GPR0)

General Purpose Register 0
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_GPR0 DDRPHYC_GPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPR0

GPR0 : GPR0
bits : 0 - 31 (32 bit)
access : read-write


DDRPHYC_GPR1 (GPR1)

General Purpose Register register 1
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_GPR1 DDRPHYC_GPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPR1

GPR1 : GPR1
bits : 0 - 31 (32 bit)
access : read-write


DDRPHYC_PTR0 (PTR0)

PTR0 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_PTR0 DDRPHYC_PTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDLLSRST TDLLLOCK TITMSRST

TDLLSRST : TDLLSRST
bits : 0 - 5 (6 bit)
access : read-write

TDLLLOCK : TDLLLOCK
bits : 6 - 17 (12 bit)
access : read-write

TITMSRST : TITMSRST
bits : 18 - 21 (4 bit)
access : read-write


DDRPHYC_ZQ0CR0 (ZQ0CR0)

ZQ0CR0 register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ZQ0CR0 DDRPHYC_ZQ0CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZDATA ZDEN ZCALBYP ZCAL ZQPD

ZDATA : ZDATA
bits : 0 - 19 (20 bit)
access : read-write

ZDEN : ZDEN
bits : 28 - 28 (1 bit)
access : read-write

ZCALBYP : ZCALBYP
bits : 29 - 29 (1 bit)
access : read-write

ZCAL : ZCAL
bits : 30 - 30 (1 bit)
access : read-write

ZQPD : ZQPD
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_ZQ0CR1 (ZQ0CR1)

ZQ0CR1 register
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ZQ0CR1 DDRPHYC_ZQ0CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ZPROG

ZPROG : ZPROG
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x1 : B_0x1

120ohm

0x5 : B_0x5

60ohm

0x8 : B_0x8

40ohm

0xB : B_0xB

40ohm

0xD : B_0xD

34ohm

End of enumeration elements list.


DDRPHYC_ZQ0SR0 (ZQ0SR0)

ZQ0SR0 register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ZQ0SR0 DDRPHYC_ZQ0SR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZCTRL ZERR ZDONE

ZCTRL : ZCTRL
bits : 0 - 19 (20 bit)
access : read-only

ZERR : ZERR
bits : 30 - 30 (1 bit)
access : read-only

ZDONE : ZDONE
bits : 31 - 31 (1 bit)
access : read-only


DDRPHYC_ZQ0SR1 (ZQ0SR1)

ZQ0SR1 register
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ZQ0SR1 DDRPHYC_ZQ0SR1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ZPD ZPU OPD OPU

ZPD : ZPD
bits : 0 - 1 (2 bit)
access : read-only

ZPU : ZPU
bits : 2 - 3 (2 bit)
access : read-only

OPD : OPD
bits : 4 - 5 (2 bit)
access : read-only

OPU : OPU
bits : 6 - 7 (2 bit)
access : read-only


DDRPHYC_PTR1 (PTR1)

PTR1 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_PTR1 DDRPHYC_PTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDINIT0 TDINIT1

TDINIT0 : TDINIT0
bits : 0 - 18 (19 bit)
access : read-write

TDINIT1 : TDINIT1
bits : 19 - 26 (8 bit)
access : read-write


DDRPHYC_DX0GCR (DX0GCR)

DX 0 GCR register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX0GCR DDRPHYC_DX0GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DXEN DQSODT DQODT DXIOM DXPDD DXPDR DQSRPD DSEN DQSRTT DQRTT RTTOH RTTOAL R0RVSL

DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write

DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write

DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write

DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write

DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write

DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write

DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write

DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write

DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write

DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write

RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write

RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write

R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write


DDRPHYC_DX0GSR0 (DX0GSR0)

DX 0 GSR0 register
address_offset : 0x1C4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX0GSR0 DDRPHYC_DX0GSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTDONE DTERR DTIERR DTPASS

DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only

DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only

DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only

DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only


DDRPHYC_DX0GSR1 (DX0GSR1)

DX 0 GSR1 register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX0GSR1 DDRPHYC_DX0GSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFTERR DQSDFT RVERR RVIERR RVPASS

DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only

DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only

RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only

RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only

RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only


DDRPHYC_DX0DLLCR (DX0DLLCR)

DX 0 DLLCR register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX0DLLCR DDRPHYC_DX0DLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFBDLY SFWDLY MFBDLY MFWDLY SSTART SDPHASE ATESTEN SDLBMODE DLLSRST DLLDIS

SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write

SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write

MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write

MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write

SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write

SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write

ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write

SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write

DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write

DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DX0DQTR (DX0DQTR)

DX 0 DQTR register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX0DQTR DDRPHYC_DX0DQTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQDLY0 DQDLY1 DQDLY2 DQDLY3 DQDLY4 DQDLY5 DQDLY6 DQDLY7

DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write

DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write

DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write

DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write

DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write

DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write

DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write

DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_DX0DQSTR (DX0DQSTR)

DX 0 DQSTR register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX0DQSTR DDRPHYC_DX0DQSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0DGSL R0DGPS DQSDLY DQSNDLY DMDLY

R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write

R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write

DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write

DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write

DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write


DDRPHYC_PTR2 (PTR2)

PTR2 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_PTR2 DDRPHYC_PTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDINIT2 TDINIT3

TDINIT2 : TDINIT2
bits : 0 - 16 (17 bit)
access : read-write

TDINIT3 : TDINIT3
bits : 17 - 26 (10 bit)
access : read-write


DDRPHYC_DX1GCR (DX1GCR)

DX 1 GCR register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX1GCR DDRPHYC_DX1GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DXEN DQSODT DQODT DXIOM DXPDD DXPDR DQSRPD DSEN DQSRTT DQRTT RTTOH RTTOAL R0RVSL

DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write

DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write

DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write

DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write

DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write

DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write

DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write

DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write

DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write

DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write

RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write

RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write

R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write


DDRPHYC_DX1GSR0 (DX1GSR0)

DX 1 GSR0 register
address_offset : 0x204 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX1GSR0 DDRPHYC_DX1GSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTDONE DTERR DTIERR DTPASS

DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only

DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only

DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only

DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only


DDRPHYC_DX1GSR1 (DX1GSR1)

DX 1 GSR1 register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX1GSR1 DDRPHYC_DX1GSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFTERR DQSDFT RVERR RVIERR RVPASS

DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only

DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only

RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only

RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only

RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only


DDRPHYC_DX1DLLCR (DX1DLLCR)

DX 1 DLLCR register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX1DLLCR DDRPHYC_DX1DLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFBDLY SFWDLY MFBDLY MFWDLY SSTART SDPHASE ATESTEN SDLBMODE DLLSRST DLLDIS

SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write

SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write

MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write

MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write

SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write

SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write

ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write

SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write

DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write

DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DX1DQTR (DX1DQTR)

DX 1 DQTR register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX1DQTR DDRPHYC_DX1DQTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQDLY0 DQDLY1 DQDLY2 DQDLY3 DQDLY4 DQDLY5 DQDLY6 DQDLY7

DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write

DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write

DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write

DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write

DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write

DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write

DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write

DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_DX1DQSTR (DX1DQSTR)

DX 1 DQSTR register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX1DQSTR DDRPHYC_DX1DQSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0DGSL R0DGPS DQSDLY DQSNDLY DMDLY

R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write

R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write

DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write

DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write

DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write


DDRPHYC_ACIOCR (ACIOCR)

ACIOCR register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ACIOCR DDRPHYC_ACIOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACIOM ACOE ACODT ACPDD ACPDR CKODT CKPDD CKPDR RANKODT CSPDD RANKPDR RSTODT RSTPDD RSTPDR RSTIOM ACSR

ACIOM : ACIOM
bits : 0 - 0 (1 bit)
access : read-write

ACOE : ACOE
bits : 1 - 1 (1 bit)
access : read-write

ACODT : ACODT
bits : 2 - 2 (1 bit)
access : read-write

ACPDD : ACPDD
bits : 3 - 3 (1 bit)
access : read-write

ACPDR : ACPDR
bits : 4 - 4 (1 bit)
access : read-write

CKODT : CKODT
bits : 5 - 7 (3 bit)
access : read-write

CKPDD : CKPDD
bits : 8 - 10 (3 bit)
access : read-write

CKPDR : CKPDR
bits : 11 - 13 (3 bit)
access : read-write

RANKODT : RANKODT
bits : 14 - 14 (1 bit)
access : read-write

CSPDD : CSPDD
bits : 18 - 18 (1 bit)
access : read-write

RANKPDR : RANKPDR
bits : 22 - 22 (1 bit)
access : read-write

RSTODT : RSTODT
bits : 26 - 26 (1 bit)
access : read-write

RSTPDD : RSTPDD
bits : 27 - 27 (1 bit)
access : read-write

RSTPDR : RSTPDR
bits : 28 - 28 (1 bit)
access : read-write

RSTIOM : RSTIOM
bits : 29 - 29 (1 bit)
access : read-write

ACSR : ACSR
bits : 30 - 31 (2 bit)
access : read-write


DDRPHYC_DX2GCR (DX2GCR)

DX 2 GCR register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX2GCR DDRPHYC_DX2GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DXEN DQSODT DQODT DXIOM DXPDD DXPDR DQSRPD DSEN DQSRTT DQRTT RTTOH RTTOAL R0RVSL

DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write

DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write

DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write

DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write

DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write

DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write

DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write

DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write

DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write

DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write

RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write

RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write

R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write


DDRPHYC_DX2GSR0 (DX2GSR0)

DX 2 GSR0 register
address_offset : 0x244 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX2GSR0 DDRPHYC_DX2GSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTDONE DTERR DTIERR DTPASS

DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only

DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only

DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only

DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only


DDRPHYC_DX2GSR1 (DX2GSR1)

DX 2 GSR1 register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX2GSR1 DDRPHYC_DX2GSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFTERR DQSDFT RVERR RVIERR RVPASS

DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only

DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only

RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only

RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only

RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only


DDRPHYC_DX2DLLCR (DX2DLLCR)

DX 2 DLLCR register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX2DLLCR DDRPHYC_DX2DLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFBDLY SFWDLY MFBDLY MFWDLY SSTART SDPHASE ATESTEN SDLBMODE DLLSRST DLLDIS

SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write

SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write

MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write

MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write

SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write

SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write

ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write

SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write

DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write

DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DX2DQTR (DX2DQTR)

DX 2 DQTR register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX2DQTR DDRPHYC_DX2DQTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQDLY0 DQDLY1 DQDLY2 DQDLY3 DQDLY4 DQDLY5 DQDLY6 DQDLY7

DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write

DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write

DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write

DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write

DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write

DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write

DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write

DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_DX2DQSTR (DX2DQSTR)

DX 2 DQSTR register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX2DQSTR DDRPHYC_DX2DQSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0DGSL R0DGPS DQSDLY DQSNDLY DMDLY

R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write

R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write

DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write

DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write

DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write


DDRPHYC_DXCCR (DXCCR)

DXCCR register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DXCCR DDRPHYC_DXCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DXODT DXIOM DXPDD DXPDR DQSRES DQSNRES DQSNRST RVSEL AWDT

DXODT : DXODT
bits : 0 - 0 (1 bit)
access : read-write

DXIOM : DXIOM
bits : 1 - 1 (1 bit)
access : read-write

DXPDD : DXPDD
bits : 2 - 2 (1 bit)
access : read-write

DXPDR : DXPDR
bits : 3 - 3 (1 bit)
access : read-write

DQSRES : DQSRES
bits : 4 - 7 (4 bit)
access : read-write

DQSNRES : DQSNRES
bits : 8 - 11 (4 bit)
access : read-write

DQSNRST : DQSNRST
bits : 14 - 14 (1 bit)
access : read-write

RVSEL : RVSEL
bits : 15 - 15 (1 bit)
access : read-write

AWDT : AWDT
bits : 16 - 16 (1 bit)
access : read-write


DDRPHYC_DX3GCR (DX3GCR)

DX 3 GCR register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX3GCR DDRPHYC_DX3GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DXEN DQSODT DQODT DXIOM DXPDD DXPDR DQSRPD DSEN DQSRTT DQRTT RTTOH RTTOAL R0RVSL

DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write

DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write

DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write

DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write

DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write

DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write

DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write

DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write

DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write

DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write

RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write

RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write

R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write


DDRPHYC_DX3GSR0 (DX3GSR0)

DX 3 GSR0 register
address_offset : 0x284 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX3GSR0 DDRPHYC_DX3GSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTDONE DTERR DTIERR DTPASS

DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only

DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only

DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only

DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only


DDRPHYC_DX3GSR1 (DX3GSR1)

DX 3 GSR1 register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX3GSR1 DDRPHYC_DX3GSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFTERR DQSDFT RVERR RVIERR RVPASS

DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only

DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only

RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only

RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only

RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only


DDRPHYC_DX3DLLCR (DX3DLLCR)

DX 3 DLLCR register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX3DLLCR DDRPHYC_DX3DLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFBDLY SFWDLY MFBDLY MFWDLY SSTART SDPHASE ATESTEN SDLBMODE DLLSRST DLLDIS

SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write

SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write

MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write

MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write

SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write

SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write

ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write

SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write

DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write

DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DX3DQTR (DX3DQTR)

DX 3 DQTR register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX3DQTR DDRPHYC_DX3DQTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQDLY0 DQDLY1 DQDLY2 DQDLY3 DQDLY4 DQDLY5 DQDLY6 DQDLY7

DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write

DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write

DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write

DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write

DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write

DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write

DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write

DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_DX3DQSTR (DX3DQSTR)

DX 3 DQSTR register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DX3DQSTR DDRPHYC_DX3DQSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0DGSL R0DGPS DQSDLY DQSNDLY DMDLY

R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write

R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write

DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write

DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write

DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write


DDRPHYC_DSGCR (DSGCR)

DSGCR register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DSGCR DDRPHYC_DSGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PUREN BDISEN ZUEN LPIOPD LPDLLPD DQSGX DQSGE NOBUB FXDLAT CKEPDD ODTPDD NL2PD NL2OE TPDPD TPDOE CKOE ODTOE RSTOE CKEOE

PUREN : PUREN
bits : 0 - 0 (1 bit)
access : read-write

BDISEN : BDISEN
bits : 1 - 1 (1 bit)
access : read-write

ZUEN : ZUEN
bits : 2 - 2 (1 bit)
access : read-write

LPIOPD : LPIOPD
bits : 3 - 3 (1 bit)
access : read-write

LPDLLPD : LPDLLPD
bits : 4 - 4 (1 bit)
access : read-write

DQSGX : DQSGX
bits : 5 - 7 (3 bit)
access : read-write

DQSGE : DQSGE
bits : 8 - 10 (3 bit)
access : read-write

NOBUB : NOBUB
bits : 11 - 11 (1 bit)
access : read-write

FXDLAT : FXDLAT
bits : 12 - 12 (1 bit)
access : read-write

CKEPDD : CKEPDD
bits : 16 - 16 (1 bit)
access : read-write

ODTPDD : ODTPDD
bits : 20 - 20 (1 bit)
access : read-write

NL2PD : NL2PD
bits : 24 - 24 (1 bit)
access : read-write

NL2OE : NL2OE
bits : 25 - 25 (1 bit)
access : read-write

TPDPD : TPDPD
bits : 26 - 26 (1 bit)
access : read-write

TPDOE : TPDOE
bits : 27 - 27 (1 bit)
access : read-write

CKOE : CKOE
bits : 28 - 28 (1 bit)
access : read-write

ODTOE : ODTOE
bits : 29 - 29 (1 bit)
access : read-write

RSTOE : RSTOE
bits : 30 - 30 (1 bit)
access : read-write

CKEOE : CKEOE
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DCR (DCR)

DCR register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCR DDRPHYC_DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRMD DDR8BNK PDQ MPRDQ DDRTYPE NOSRA DDR2T UDIMM RDIMM TPD

DDRMD : DDRMD
bits : 0 - 2 (3 bit)
access : read-write

DDR8BNK : DDR8BNK
bits : 3 - 3 (1 bit)
access : read-write

PDQ : PDQ
bits : 4 - 6 (3 bit)
access : read-write

MPRDQ : MPRDQ
bits : 7 - 7 (1 bit)
access : read-write

DDRTYPE : DDRTYPE
bits : 8 - 9 (2 bit)
access : read-write

NOSRA : NOSRA
bits : 27 - 27 (1 bit)
access : read-write

DDR2T : DDR2T
bits : 28 - 28 (1 bit)
access : read-write

UDIMM : UDIMM
bits : 29 - 29 (1 bit)
access : read-write

RDIMM : RDIMM
bits : 30 - 30 (1 bit)
access : read-write

TPD : TPD
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DTPR0 (DTPR0)

DTPR0 register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DTPR0 DDRPHYC_DTPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRD TRTP TWTR TRP TRCD TRAS TRRD TRC TCCD

TMRD : TMRD
bits : 0 - 1 (2 bit)
access : read-write

TRTP : TRTP
bits : 2 - 4 (3 bit)
access : read-write

TWTR : TWTR
bits : 5 - 7 (3 bit)
access : read-write

TRP : TRP
bits : 8 - 11 (4 bit)
access : read-write

TRCD : TRCD
bits : 12 - 15 (4 bit)
access : read-write

TRAS : TRAS
bits : 16 - 20 (5 bit)
access : read-write

TRRD : TRRD
bits : 21 - 24 (4 bit)
access : read-write

TRC : TRC
bits : 25 - 30 (6 bit)
access : read-write

TCCD : TCCD
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DTPR1 (DTPR1)

DTPR1 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DTPR1 DDRPHYC_DTPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAOND TRTW TFAW TMOD TRTODT TRFC TDQSCKMIN TDQSCKMAX

TAOND : TAOND
bits : 0 - 1 (2 bit)
access : read-write

TRTW : TRTW
bits : 2 - 2 (1 bit)
access : read-write

TFAW : TFAW
bits : 3 - 8 (6 bit)
access : read-write

TMOD : TMOD
bits : 9 - 10 (2 bit)
access : read-write

TRTODT : TRTODT
bits : 11 - 11 (1 bit)
access : read-write

TRFC : TRFC
bits : 16 - 23 (8 bit)
access : read-write

TDQSCKMIN : TDQSCKMIN
bits : 24 - 26 (3 bit)
access : read-write

TDQSCKMAX : TDQSCKMAX
bits : 27 - 29 (3 bit)
access : read-write


DDRPHYC_DTPR2 (DTPR2)

DTPR2 register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DTPR2 DDRPHYC_DTPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXS TXP TCKE TDLLK

TXS : TXS
bits : 0 - 9 (10 bit)
access : read-write

TXP : TXP
bits : 10 - 14 (5 bit)
access : read-write

TCKE : TCKE
bits : 15 - 18 (4 bit)
access : read-write

TDLLK : TDLLK
bits : 19 - 28 (10 bit)
access : read-write


DDRPHYC_PIR (PIR)

PIR register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_PIR DDRPHYC_PIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT DLLSRST DLLLOCK ZCAL ITMSRST DRAMRST DRAMINIT QSTRN RVTRN ICPC DLLBYP CTLDINIT CLRSR LOCKBYP ZCALBYP INITBYP

INIT : INIT
bits : 0 - 0 (1 bit)
access : write-only

DLLSRST : DLLSRST
bits : 1 - 1 (1 bit)
access : write-only

DLLLOCK : DLLLOCK
bits : 2 - 2 (1 bit)
access : write-only

ZCAL : ZCAL
bits : 3 - 3 (1 bit)
access : write-only

ITMSRST : ITMSRST
bits : 4 - 4 (1 bit)
access : write-only

DRAMRST : DRAMRST
bits : 5 - 5 (1 bit)
access : write-only

DRAMINIT : DRAMINIT
bits : 6 - 6 (1 bit)
access : write-only

QSTRN : QSTRN
bits : 7 - 7 (1 bit)
access : write-only

RVTRN : RVTRN
bits : 8 - 8 (1 bit)
access : write-only

ICPC : ICPC
bits : 16 - 16 (1 bit)
access : write-only

DLLBYP : DLLBYP
bits : 17 - 17 (1 bit)
access : write-only

CTLDINIT : CTLDINIT
bits : 18 - 18 (1 bit)
access : write-only

CLRSR : CLRSR
bits : 28 - 28 (1 bit)
access : write-only

LOCKBYP : LOCKBYP
bits : 29 - 29 (1 bit)
access : write-only

ZCALBYP : ZCALBYP
bits : 30 - 30 (1 bit)
access : write-only

INITBYP : INITBYP
bits : 31 - 31 (1 bit)
access : write-only


DDRPHYC_MR0 (MR0)

MR0 register for DDR3
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_MR0 DDRPHYC_MR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BL CL0 BT CL TM DR WR PD RSVD

BL : BL
bits : 0 - 1 (2 bit)
access : read-write

CL0 : CL0
bits : 2 - 2 (1 bit)
access : read-write

BT : BT
bits : 3 - 3 (1 bit)
access : read-write

CL : CL
bits : 4 - 6 (3 bit)
access : read-write

TM : TM
bits : 7 - 7 (1 bit)
access : read-write

DR : DR
bits : 8 - 8 (1 bit)
access : read-write

WR : WR
bits : 9 - 11 (3 bit)
access : read-write

PD : PD
bits : 12 - 12 (1 bit)
access : read-write

RSVD : RSVD
bits : 13 - 15 (3 bit)
access : read-write


DDRPHYC_MR1 (MR1)

MR1 register for LPDDR2
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_MR1 DDRPHYC_MR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BL BT WC NWR

BL : BL
bits : 0 - 2 (3 bit)
access : read-write

BT : BT
bits : 3 - 3 (1 bit)
access : read-write

WC : WC
bits : 4 - 4 (1 bit)
access : read-write

NWR : NWR
bits : 5 - 7 (3 bit)
access : read-write


DDRPHYC_MR2 (MR2)

MR2 register for LPDDR2
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_MR2 DDRPHYC_MR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLWL

RLWL : RLWL
bits : 0 - 2 (3 bit)
access : read-write


DDRPHYC_MR3 (MR3)

MR3 register for DDR3
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_MR3 DDRPHYC_MR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MPRLOC MPR

MPRLOC : MPRLOC
bits : 0 - 1 (2 bit)
access : read-write

MPR : MPR
bits : 2 - 2 (1 bit)
access : read-write


DDRPHYC_ODTCR (ODTCR)

ODTCR register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_ODTCR DDRPHYC_ODTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDODT0 RDODT1 RDODT2 RDODT3 WRODT0 WRODT1 WRODT2 WRODT3

RDODT0 : RDODT0
bits : 0 - 3 (4 bit)
access : read-write

RDODT1 : RDODT1
bits : 4 - 7 (4 bit)
access : read-write

RDODT2 : RDODT2
bits : 8 - 11 (4 bit)
access : read-write

RDODT3 : RDODT3
bits : 12 - 15 (4 bit)
access : read-write

WRODT0 : WRODT0
bits : 16 - 19 (4 bit)
access : read-write

WRODT1 : WRODT1
bits : 20 - 23 (4 bit)
access : read-write

WRODT2 : WRODT2
bits : 24 - 27 (4 bit)
access : read-write

WRODT3 : WRODT3
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_DTAR (DTAR)

DTAR register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DTAR DDRPHYC_DTAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCOL DTROW DTBANK DTMPR

DTCOL : DTCOL
bits : 0 - 11 (12 bit)
access : read-write

DTROW : DTROW
bits : 12 - 27 (16 bit)
access : read-write

DTBANK : DTBANK
bits : 28 - 30 (3 bit)
access : read-write

DTMPR : DTMPR
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_DTDR0 (DTDR0)

DTDR0 register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DTDR0 DDRPHYC_DTDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTBYTE0 DTBYTE1 DTBYTE2 DTBYTE3

DTBYTE0 : DTBYTE0
bits : 0 - 7 (8 bit)
access : read-write

DTBYTE1 : DTBYTE1
bits : 8 - 15 (8 bit)
access : read-write

DTBYTE2 : DTBYTE2
bits : 16 - 23 (8 bit)
access : read-write

DTBYTE3 : DTBYTE3
bits : 24 - 31 (8 bit)
access : read-write


DDRPHYC_DTDR1 (DTDR1)

DTDR1 register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DTDR1 DDRPHYC_DTDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTBYTE4 DTBYTE5 DTBYTE6 DTBYTE7

DTBYTE4 : DTBYTE4
bits : 0 - 7 (8 bit)
access : read-write

DTBYTE5 : DTBYTE5
bits : 8 - 15 (8 bit)
access : read-write

DTBYTE6 : DTBYTE6
bits : 16 - 23 (8 bit)
access : read-write

DTBYTE7 : DTBYTE7
bits : 24 - 31 (8 bit)
access : read-write


DDRPHYC_PGCR (PGCR)

PGCR register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_PGCR DDRPHYC_PGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITMDMD DQSCFG DFTCMP DFTLMT DTOSEL CKEN CKDV CKINV IOLB IODDRM RANKEN ZKSEL PDDISDX RFSHDT LBDQSS LBGDQS LBMODE

ITMDMD : ITMDMD
bits : 0 - 0 (1 bit)
access : read-write

DQSCFG : DQSCFG
bits : 1 - 1 (1 bit)
access : read-write

DFTCMP : DFTCMP
bits : 2 - 2 (1 bit)
access : read-write

DFTLMT : DFTLMT
bits : 3 - 4 (2 bit)
access : read-write

DTOSEL : DTOSEL
bits : 5 - 8 (4 bit)
access : read-write

CKEN : CKEN
bits : 9 - 11 (3 bit)
access : read-write

CKDV : CKDV
bits : 12 - 13 (2 bit)
access : read-write

CKINV : CKINV
bits : 14 - 14 (1 bit)
access : read-write

IOLB : IOLB
bits : 15 - 15 (1 bit)
access : read-write

IODDRM : IODDRM
bits : 16 - 17 (2 bit)
access : read-write

RANKEN : RANKEN
bits : 18 - 21 (4 bit)
access : read-write

ZKSEL : ZKSEL
bits : 22 - 23 (2 bit)
access : read-write

PDDISDX : PDDISDX
bits : 24 - 24 (1 bit)
access : read-write

RFSHDT : RFSHDT
bits : 25 - 28 (4 bit)
access : read-write

LBDQSS : LBDQSS
bits : 29 - 29 (1 bit)
access : read-write

LBGDQS : LBGDQS
bits : 30 - 30 (1 bit)
access : read-write

LBMODE : LBMODE
bits : 31 - 31 (1 bit)
access : read-write


DDRPHYC_PGSR (PGSR)

PGSR register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_PGSR DDRPHYC_PGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDONE DLDONE ZCDDONE DIDONE DTDONE DTERR DTIERR DFTERR RVERR RVEIRR TQ

IDONE : IDONE
bits : 0 - 0 (1 bit)
access : read-only

DLDONE : DLDONE
bits : 1 - 1 (1 bit)
access : read-only

ZCDDONE : ZCDDONE
bits : 2 - 2 (1 bit)
access : read-only

DIDONE : DIDONE
bits : 3 - 3 (1 bit)
access : read-only

DTDONE : DTDONE
bits : 4 - 4 (1 bit)
access : read-only

DTERR : DTERR
bits : 5 - 5 (1 bit)
access : read-only

DTIERR : DTIERR
bits : 6 - 6 (1 bit)
access : read-only

DFTERR : DFTERR
bits : 7 - 7 (1 bit)
access : read-only

RVERR : RVERR
bits : 8 - 8 (1 bit)
access : read-only

RVEIRR : RVEIRR
bits : 9 - 9 (1 bit)
access : read-only

TQ : TQ
bits : 31 - 31 (1 bit)
access : read-only


DDRPHYC_DCUAR (DCUAR)

DCUAR register
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCUAR DDRPHYC_DCUAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWADDR CSADDR CSEL INCA ATYPE

CWADDR : CWADDR
bits : 0 - 3 (4 bit)
access : read-write

CSADDR : CSADDR
bits : 4 - 7 (4 bit)
access : read-write

CSEL : CSEL
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Command cache

0x1 : B_0x1

Expected data cache

0x2 : B_0x2

Read data cache

End of enumeration elements list.

INCA : INCA
bits : 10 - 10 (1 bit)
access : read-write

ATYPE : ATYPE
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Write access

0x1 : B_0x1

Read access

End of enumeration elements list.


DDRPHYC_DCUDR (DCUDR)

DCUDR register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCUDR DDRPHYC_DCUDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDATA

CDATA : CDATA
bits : 0 - 31 (32 bit)
access : read-write


DDRPHYC_DCURR (DCURR)

DCURR register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCURR DDRPHYC_DCURR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DINST SADDR EADDR NFAIL SONF SCOF RCEN XCEN

DINST : DINST
bits : 0 - 3 (4 bit)
access : read-write

SADDR : SADDR
bits : 4 - 7 (4 bit)
access : read-write

EADDR : EADDR
bits : 8 - 11 (4 bit)
access : read-write

NFAIL : NFAIL
bits : 12 - 19 (8 bit)
access : read-write

SONF : SONF
bits : 20 - 20 (1 bit)
access : read-write

SCOF : SCOF
bits : 21 - 21 (1 bit)
access : read-write

RCEN : RCEN
bits : 22 - 22 (1 bit)
access : read-write

XCEN : XCEN
bits : 23 - 23 (1 bit)
access : read-write


DDRPHYC_DCULR (DCULR)

DCULR register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCULR DDRPHYC_DCULR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSADDR LEADDR LCNT LFINF IDA XLEADDR

LSADDR : LSADDR
bits : 0 - 3 (4 bit)
access : read-write

LEADDR : LEADDR
bits : 4 - 7 (4 bit)
access : read-write

LCNT : LCNT
bits : 8 - 15 (8 bit)
access : read-write

LFINF : LFINF
bits : 16 - 16 (1 bit)
access : read-write

IDA : IDA
bits : 17 - 17 (1 bit)
access : read-write

XLEADDR : XLEADDR
bits : 28 - 31 (4 bit)
access : read-write


DDRPHYC_DCUGCR (DCUGCR)

DCUGCR register
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCUGCR DDRPHYC_DCUGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCSW

RCSW : RCSW
bits : 0 - 15 (16 bit)
access : read-write


DDRPHYC_DCUTPR (DCUTPR)

DCUTPR register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCUTPR DDRPHYC_DCUTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCUTO TDCUT1 TDCUT2 TDCUT3

TDCUTO : TDCUTO
bits : 0 - 7 (8 bit)
access : read-write

TDCUT1 : TDCUT1
bits : 8 - 15 (8 bit)
access : read-write

TDCUT2 : TDCUT2
bits : 16 - 23 (8 bit)
access : read-write

TDCUT3 : TDCUT3
bits : 24 - 31 (8 bit)
access : read-write


DDRPHYC_DCUSR0 (DCUSR0)

DCUSR0 register
address_offset : 0xD8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCUSR0 DDRPHYC_DCUSR0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDONE CFAIL CFULL

RDONE : RDONE
bits : 0 - 0 (1 bit)
access : read-only

CFAIL : CFAIL
bits : 1 - 1 (1 bit)
access : read-only

CFULL : CFULL
bits : 2 - 2 (1 bit)
access : read-only


DDRPHYC_DCUSR1 (DCUSR1)

DCUSR1 register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDRPHYC_DCUSR1 DDRPHYC_DCUSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDCNT FLCND LPCNT

RDCNT : RDCNT
bits : 0 - 15 (16 bit)
access : read-only

FLCND : FLCND
bits : 16 - 23 (8 bit)
access : read-only

LPCNT : LPCNT
bits : 24 - 31 (8 bit)
access : read-only



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