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DFSDM1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DFSDM_CH0CFGR1

DFSDM_CH0DATINR

DFSDM_FLT0CR1

DFSDM_FLT0CR2

DFSDM_FLT0ISR

DFSDM_FLT0ICR

DFSDM_FLT0JCHGR

DFSDM_FLT0FCR

DFSDM_FLT0JDATAR

DFSDM_FLT0RDATAR

DFSDM_FLT0AWHTR

DFSDM_FLT0AWLTR

DFSDM_FLT0AWSR

DFSDM_FLT0AWCFR

DFSDM_FLT0EXMAX

DFSDM_FLT0EXMIN

DFSDM_FLT0CNVTIMR

DFSDM_FLT1CR1

DFSDM_FLT1CR2

DFSDM_FLT1ISR

DFSDM_FLT1ICR

DFSDM_FLT1JCHGR

DFSDM_FLT1FCR

DFSDM_FLT1JDATAR

DFSDM_FLT1RDATAR

DFSDM_FLT1AWHTR

DFSDM_FLT1AWLTR

DFSDM_FLT1AWSR

DFSDM_FLT1AWCFR

DFSDM_FLT1EXMAX

DFSDM_FLT1EXMIN

DFSDM_FLT1CNVTIMR

DFSDM_CH1CFGR1

DFSDM_FLT2CR1

DFSDM_FLT2CR2

DFSDM_FLT2ISR

DFSDM_FLT2ICR

DFSDM_FLT2JCHGR

DFSDM_FLT2FCR

DFSDM_FLT2JDATAR

DFSDM_FLT2RDATAR

DFSDM_FLT2AWHTR

DFSDM_FLT2AWLTR

DFSDM_FLT2AWSR

DFSDM_FLT2AWCFR

DFSDM_FLT2EXMAX

DFSDM_FLT2EXMIN

DFSDM_FLT2CNVTIMR

DFSDM_CH1CFGR2

DFSDM_CH1AWSCDR

DFSDM_FLT3CR1

DFSDM_FLT3CR2

DFSDM_FLT3ISR

DFSDM_FLT3ICR

DFSDM_FLT3JCHGR

DFSDM_FLT3FCR

DFSDM_FLT3JDATAR

DFSDM_FLT3RDATAR

DFSDM_FLT3AWHTR

DFSDM_FLT3AWLTR

DFSDM_FLT3AWSR

DFSDM_FLT3AWCFR

DFSDM_FLT3EXMAX

DFSDM_FLT3EXMIN

DFSDM_FLT3CNVTIMR

DFSDM_CH1WDATR

DFSDM_CH1DATINR

DFSDM_CH0CFGR2

DFSDM_CH2CFGR1

DFSDM_CH2CFGR2

DFSDM_CH2AWSCDR

DFSDM_CH2WDATR

DFSDM_CH2DATINR

DFSDM_CH3CFGR1

DFSDM_CH3CFGR2

DFSDM_CH3AWSCDR

DFSDM_CH3WDATR

DFSDM_CH3DATINR

DFSDM_CH0AWSCDR

DFSDM_CH4CFGR1

DFSDM_CH4CFGR2

DFSDM_CH4AWSCDR

DFSDM_CH4WDATR

DFSDM_CH4DATINR

DFSDM_CH5CFGR1

DFSDM_CH5CFGR2

DFSDM_CH5AWSCDR

DFSDM_CH5WDATR

DFSDM_CH5DATINR

DFSDM_CH0WDATR

DFSDM_CH6CFGR1

DFSDM_CH6CFGR2

DFSDM_CH6AWSCDR

DFSDM_CH6WDATR

DFSDM_CH6DATINR

DFSDM_CH7CFGR1

DFSDM_CH7CFGR2

DFSDM_CH7AWSCDR

DFSDM_CH7WDATR

DFSDM_CH7DATINR


DFSDM_CH0CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0CFGR1 DFSDM_CH0CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH0DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0DATINR DFSDM_CH0DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_FLT0CR1

DFSDM control register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CR1 DFSDM_FLT0CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.

0x1 : B_0x1

DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.

End of enumeration elements list.

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect.

0x1 : B_0x1

Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1.

End of enumeration elements list.

JSYNC : JSYNC
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch an injected conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

End of enumeration elements list.

JSCAN : JSCAN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.

0x1 : B_0x1

The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.

End of enumeration elements list.

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read injected data

0x1 : B_0x1

The DMA channel is enabled to read injected data

End of enumeration elements list.

JEXTSEL : JEXTSEL
bits : 8 - 10 (3 bit)
access : read-write

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Trigger detection is disabled

0x1 : B_0x1

Each rising edge on the selected trigger makes a request to launch an injected conversion

0x2 : B_0x2

Each falling edge on the selected trigger makes a request to launch an injected conversion

0x3 : B_0x3

Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

End of enumeration elements list.

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1.

End of enumeration elements list.

RCONT : RCONT
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The regular channel is converted just once for each conversion request

0x1 : B_0x1

The regular channel is converted repeatedly after each conversion request

End of enumeration elements list.

RSYNC : RSYNC
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch a regular conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

End of enumeration elements list.

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read regular data

0x1 : B_0x1

The DMA channel is enabled to read regular data

End of enumeration elements list.

RCH : RCH
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel 0 is selected as the regular channel

0x1 : B_0x1

Channel 1 is selected as the regular channel

0x7 : B_0x7

Channel 7 is selected as the regular channel

End of enumeration elements list.

FAST : FAST
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Fast conversion mode disabled

0x1 : B_0x1

Fast conversion mode enabled

End of enumeration elements list.

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift

0x1 : B_0x1

Analog watchdog on channel transceivers value (after watchdog filter)

End of enumeration elements list.


DFSDM_FLT0CR2

DFSDM control register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CR2 DFSDM_FLT0CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected end of conversion interrupt is disabled

0x1 : B_0x1

Injected end of conversion interrupt is enabled

End of enumeration elements list.

REOCIE : REOCIE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular end of conversion interrupt is disabled

0x1 : B_0x1

Regular end of conversion interrupt is enabled

End of enumeration elements list.

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected data overrun interrupt is disabled

0x1 : B_0x1

Injected data overrun interrupt is enabled

End of enumeration elements list.

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular data overrun interrupt is disabled

0x1 : B_0x1

Regular data overrun interrupt is enabled

End of enumeration elements list.

AWDIE : AWDIE
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog interrupt is disabled

0x1 : B_0x1

Analog watchdog interrupt is enabled

End of enumeration elements list.

SCDIE : SCDIE
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

short-circuit detector interrupt is disabled

0x1 : B_0x1

short-circuit detector interrupt is enabled

End of enumeration elements list.

CKABIE : CKABIE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Detection of channel input clock absence interrupt is disabled

0x1 : B_0x1

Detection of channel input clock absence interrupt is enabled

End of enumeration elements list.

EXCH : EXCH
bits : 8 - 15 (8 bit)
access : read-write

AWDCH : AWDCH
bits : 16 - 23 (8 bit)
access : read-write


DFSDM_FLT0ISR

DFSDM interrupt and status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0ISR DFSDM_FLT0ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion has completed

0x1 : B_0x1

An injected conversion has completed and its data may be read

End of enumeration elements list.

REOCF : REOCF
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion has completed

0x1 : B_0x1

A regular conversion has completed and its data may be read

End of enumeration elements list.

JOVRF : JOVRF
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion overrun has occurred

0x1 : B_0x1

An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns

End of enumeration elements list.

ROVRF : ROVRF
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion overrun has occurred

0x1 : B_0x1

A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns

End of enumeration elements list.

AWDF : AWDF
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No Analog watchdog event occurred

0x1 : B_0x1

The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.

End of enumeration elements list.

JCIP : JCIP
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the injected channel group (neither by software nor by trigger) has been issued

0x1 : B_0x1

The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection

End of enumeration elements list.

RCIP : RCIP
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the regular channel has been issued

0x1 : B_0x1

The conversion of the regular channel is in progress or a request for a regular conversion is pending

End of enumeration elements list.

CKABF : CKABF
bits : 16 - 23 (8 bit)
access : read-only

SCDF : SCDF
bits : 24 - 31 (8 bit)
access : read-only


DFSDM_FLT0ICR

DFSDM interrupt flag clear register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0ICR DFSDM_FLT0ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
access : read-write

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
access : read-write


DFSDM_FLT0JCHGR

DFSDM injected channel group selection register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0JCHGR DFSDM_FLT0JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)
access : read-write


DFSDM_FLT0FCR

DFSDM filter control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0FCR DFSDM_FLT0FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)
access : read-write

FOSR : FOSR
bits : 16 - 25 (10 bit)
access : read-write

FORD : FORD
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

0x4 : B_0x4

Sinc4 filter type

0x5 : B_0x5

Sinc5 filter type

End of enumeration elements list.


DFSDM_FLT0JDATAR

DFSDM data register for injected group
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0JDATAR DFSDM_FLT0JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)
access : read-only

JDATA : JDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT0RDATAR

DFSDM data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0RDATAR DFSDM_FLT0RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)
access : read-only

RPEND : RPEND
bits : 4 - 4 (1 bit)
access : read-only

RDATA : RDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT0AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWHTR DFSDM_FLT0AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)
access : read-write

AWHT : AWHT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT0AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWLTR DFSDM_FLT0AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)
access : read-write

AWLT : AWLT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT0AWSR

DFSDM analog watchdog status register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWSR DFSDM_FLT0AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)
access : read-only

AWHTF : AWHTF
bits : 8 - 15 (8 bit)
access : read-only


DFSDM_FLT0AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWCFR DFSDM_FLT0AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
access : read-write

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
access : read-write


DFSDM_FLT0EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0EXMAX DFSDM_FLT0EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
access : read-only

EXMAX : EXMAX
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT0EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0EXMIN DFSDM_FLT0EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT0CNVTIMR

DFSDM conversion timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CNVTIMR DFSDM_FLT0CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
access : read-only


DFSDM_FLT1CR1

DFSDM control register 1
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CR1 DFSDM_FLT1CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.

0x1 : B_0x1

DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.

End of enumeration elements list.

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect.

0x1 : B_0x1

Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1.

End of enumeration elements list.

JSYNC : JSYNC
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch an injected conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

End of enumeration elements list.

JSCAN : JSCAN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.

0x1 : B_0x1

The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.

End of enumeration elements list.

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read injected data

0x1 : B_0x1

The DMA channel is enabled to read injected data

End of enumeration elements list.

JEXTSEL : JEXTSEL
bits : 8 - 10 (3 bit)
access : read-write

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Trigger detection is disabled

0x1 : B_0x1

Each rising edge on the selected trigger makes a request to launch an injected conversion

0x2 : B_0x2

Each falling edge on the selected trigger makes a request to launch an injected conversion

0x3 : B_0x3

Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

End of enumeration elements list.

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1.

End of enumeration elements list.

RCONT : RCONT
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The regular channel is converted just once for each conversion request

0x1 : B_0x1

The regular channel is converted repeatedly after each conversion request

End of enumeration elements list.

RSYNC : RSYNC
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch a regular conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

End of enumeration elements list.

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read regular data

0x1 : B_0x1

The DMA channel is enabled to read regular data

End of enumeration elements list.

RCH : RCH
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel 0 is selected as the regular channel

0x1 : B_0x1

Channel 1 is selected as the regular channel

0x7 : B_0x7

Channel 7 is selected as the regular channel

End of enumeration elements list.

FAST : FAST
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Fast conversion mode disabled

0x1 : B_0x1

Fast conversion mode enabled

End of enumeration elements list.

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift

0x1 : B_0x1

Analog watchdog on channel transceivers value (after watchdog filter)

End of enumeration elements list.


DFSDM_FLT1CR2

DFSDM control register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CR2 DFSDM_FLT1CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected end of conversion interrupt is disabled

0x1 : B_0x1

Injected end of conversion interrupt is enabled

End of enumeration elements list.

REOCIE : REOCIE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular end of conversion interrupt is disabled

0x1 : B_0x1

Regular end of conversion interrupt is enabled

End of enumeration elements list.

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected data overrun interrupt is disabled

0x1 : B_0x1

Injected data overrun interrupt is enabled

End of enumeration elements list.

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular data overrun interrupt is disabled

0x1 : B_0x1

Regular data overrun interrupt is enabled

End of enumeration elements list.

AWDIE : AWDIE
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog interrupt is disabled

0x1 : B_0x1

Analog watchdog interrupt is enabled

End of enumeration elements list.

SCDIE : SCDIE
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

short-circuit detector interrupt is disabled

0x1 : B_0x1

short-circuit detector interrupt is enabled

End of enumeration elements list.

CKABIE : CKABIE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Detection of channel input clock absence interrupt is disabled

0x1 : B_0x1

Detection of channel input clock absence interrupt is enabled

End of enumeration elements list.

EXCH : EXCH
bits : 8 - 15 (8 bit)
access : read-write

AWDCH : AWDCH
bits : 16 - 23 (8 bit)
access : read-write


DFSDM_FLT1ISR

DFSDM interrupt and status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1ISR DFSDM_FLT1ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion has completed

0x1 : B_0x1

An injected conversion has completed and its data may be read

End of enumeration elements list.

REOCF : REOCF
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion has completed

0x1 : B_0x1

A regular conversion has completed and its data may be read

End of enumeration elements list.

JOVRF : JOVRF
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion overrun has occurred

0x1 : B_0x1

An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns

End of enumeration elements list.

ROVRF : ROVRF
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion overrun has occurred

0x1 : B_0x1

A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns

End of enumeration elements list.

AWDF : AWDF
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No Analog watchdog event occurred

0x1 : B_0x1

The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.

End of enumeration elements list.

JCIP : JCIP
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the injected channel group (neither by software nor by trigger) has been issued

0x1 : B_0x1

The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection

End of enumeration elements list.

RCIP : RCIP
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the regular channel has been issued

0x1 : B_0x1

The conversion of the regular channel is in progress or a request for a regular conversion is pending

End of enumeration elements list.

CKABF : CKABF
bits : 16 - 23 (8 bit)
access : read-only

SCDF : SCDF
bits : 24 - 31 (8 bit)
access : read-only


DFSDM_FLT1ICR

DFSDM interrupt flag clear register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1ICR DFSDM_FLT1ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
access : read-write

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
access : read-write


DFSDM_FLT1JCHGR

DFSDM injected channel group selection register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1JCHGR DFSDM_FLT1JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)
access : read-write


DFSDM_FLT1FCR

DFSDM filter control register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1FCR DFSDM_FLT1FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)
access : read-write

FOSR : FOSR
bits : 16 - 25 (10 bit)
access : read-write

FORD : FORD
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

0x4 : B_0x4

Sinc4 filter type

0x5 : B_0x5

Sinc5 filter type

End of enumeration elements list.


DFSDM_FLT1JDATAR

DFSDM data register for injected group
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1JDATAR DFSDM_FLT1JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)
access : read-only

JDATA : JDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT1RDATAR

DFSDM data register for the regular channel
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1RDATAR DFSDM_FLT1RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)
access : read-only

RPEND : RPEND
bits : 4 - 4 (1 bit)
access : read-only

RDATA : RDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT1AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWHTR DFSDM_FLT1AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)
access : read-write

AWHT : AWHT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT1AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWLTR DFSDM_FLT1AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)
access : read-write

AWLT : AWLT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT1AWSR

DFSDM analog watchdog status register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWSR DFSDM_FLT1AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)
access : read-only

AWHTF : AWHTF
bits : 8 - 15 (8 bit)
access : read-only


DFSDM_FLT1AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWCFR DFSDM_FLT1AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
access : read-write

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
access : read-write


DFSDM_FLT1EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1EXMAX DFSDM_FLT1EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
access : read-only

EXMAX : EXMAX
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT1EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1EXMIN DFSDM_FLT1EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT1CNVTIMR

DFSDM conversion timer register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CNVTIMR DFSDM_FLT1CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
access : read-only


DFSDM_CH1CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1CFGR1 DFSDM_CH1CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_FLT2CR1

DFSDM control register 1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CR1 DFSDM_FLT2CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.

0x1 : B_0x1

DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.

End of enumeration elements list.

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect.

0x1 : B_0x1

Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1.

End of enumeration elements list.

JSYNC : JSYNC
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch an injected conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

End of enumeration elements list.

JSCAN : JSCAN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.

0x1 : B_0x1

The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.

End of enumeration elements list.

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read injected data

0x1 : B_0x1

The DMA channel is enabled to read injected data

End of enumeration elements list.

JEXTSEL : JEXTSEL
bits : 8 - 10 (3 bit)
access : read-write

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Trigger detection is disabled

0x1 : B_0x1

Each rising edge on the selected trigger makes a request to launch an injected conversion

0x2 : B_0x2

Each falling edge on the selected trigger makes a request to launch an injected conversion

0x3 : B_0x3

Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

End of enumeration elements list.

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1.

End of enumeration elements list.

RCONT : RCONT
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The regular channel is converted just once for each conversion request

0x1 : B_0x1

The regular channel is converted repeatedly after each conversion request

End of enumeration elements list.

RSYNC : RSYNC
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch a regular conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

End of enumeration elements list.

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read regular data

0x1 : B_0x1

The DMA channel is enabled to read regular data

End of enumeration elements list.

RCH : RCH
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel 0 is selected as the regular channel

0x1 : B_0x1

Channel 1 is selected as the regular channel

0x7 : B_0x7

Channel 7 is selected as the regular channel

End of enumeration elements list.

FAST : FAST
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Fast conversion mode disabled

0x1 : B_0x1

Fast conversion mode enabled

End of enumeration elements list.

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift

0x1 : B_0x1

Analog watchdog on channel transceivers value (after watchdog filter)

End of enumeration elements list.


DFSDM_FLT2CR2

DFSDM control register 2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CR2 DFSDM_FLT2CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected end of conversion interrupt is disabled

0x1 : B_0x1

Injected end of conversion interrupt is enabled

End of enumeration elements list.

REOCIE : REOCIE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular end of conversion interrupt is disabled

0x1 : B_0x1

Regular end of conversion interrupt is enabled

End of enumeration elements list.

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected data overrun interrupt is disabled

0x1 : B_0x1

Injected data overrun interrupt is enabled

End of enumeration elements list.

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular data overrun interrupt is disabled

0x1 : B_0x1

Regular data overrun interrupt is enabled

End of enumeration elements list.

AWDIE : AWDIE
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog interrupt is disabled

0x1 : B_0x1

Analog watchdog interrupt is enabled

End of enumeration elements list.

SCDIE : SCDIE
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

short-circuit detector interrupt is disabled

0x1 : B_0x1

short-circuit detector interrupt is enabled

End of enumeration elements list.

CKABIE : CKABIE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Detection of channel input clock absence interrupt is disabled

0x1 : B_0x1

Detection of channel input clock absence interrupt is enabled

End of enumeration elements list.

EXCH : EXCH
bits : 8 - 15 (8 bit)
access : read-write

AWDCH : AWDCH
bits : 16 - 23 (8 bit)
access : read-write


DFSDM_FLT2ISR

DFSDM interrupt and status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2ISR DFSDM_FLT2ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion has completed

0x1 : B_0x1

An injected conversion has completed and its data may be read

End of enumeration elements list.

REOCF : REOCF
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion has completed

0x1 : B_0x1

A regular conversion has completed and its data may be read

End of enumeration elements list.

JOVRF : JOVRF
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion overrun has occurred

0x1 : B_0x1

An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns

End of enumeration elements list.

ROVRF : ROVRF
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion overrun has occurred

0x1 : B_0x1

A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns

End of enumeration elements list.

AWDF : AWDF
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No Analog watchdog event occurred

0x1 : B_0x1

The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.

End of enumeration elements list.

JCIP : JCIP
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the injected channel group (neither by software nor by trigger) has been issued

0x1 : B_0x1

The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection

End of enumeration elements list.

RCIP : RCIP
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the regular channel has been issued

0x1 : B_0x1

The conversion of the regular channel is in progress or a request for a regular conversion is pending

End of enumeration elements list.

CKABF : CKABF
bits : 16 - 23 (8 bit)
access : read-only

SCDF : SCDF
bits : 24 - 31 (8 bit)
access : read-only


DFSDM_FLT2ICR

DFSDM interrupt flag clear register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2ICR DFSDM_FLT2ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
access : read-write

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
access : read-write


DFSDM_FLT2JCHGR

DFSDM injected channel group selection register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2JCHGR DFSDM_FLT2JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)
access : read-write


DFSDM_FLT2FCR

DFSDM filter control register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2FCR DFSDM_FLT2FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)
access : read-write

FOSR : FOSR
bits : 16 - 25 (10 bit)
access : read-write

FORD : FORD
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

0x4 : B_0x4

Sinc4 filter type

0x5 : B_0x5

Sinc5 filter type

End of enumeration elements list.


DFSDM_FLT2JDATAR

DFSDM data register for injected group
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2JDATAR DFSDM_FLT2JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)
access : read-only

JDATA : JDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT2RDATAR

DFSDM data register for the regular channel
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2RDATAR DFSDM_FLT2RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)
access : read-only

RPEND : RPEND
bits : 4 - 4 (1 bit)
access : read-only

RDATA : RDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT2AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWHTR DFSDM_FLT2AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)
access : read-write

AWHT : AWHT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT2AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWLTR DFSDM_FLT2AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)
access : read-write

AWLT : AWLT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT2AWSR

DFSDM analog watchdog status register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWSR DFSDM_FLT2AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)
access : read-only

AWHTF : AWHTF
bits : 8 - 15 (8 bit)
access : read-only


DFSDM_FLT2AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWCFR DFSDM_FLT2AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
access : read-write

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
access : read-write


DFSDM_FLT2EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2EXMAX DFSDM_FLT2EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
access : read-only

EXMAX : EXMAX
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT2EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2EXMIN DFSDM_FLT2EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT2CNVTIMR

DFSDM conversion timer register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CNVTIMR DFSDM_FLT2CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
access : read-only


DFSDM_CH1CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1CFGR2 DFSDM_CH1CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH1AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1AWSCDR DFSDM_CH1AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_FLT3CR1

DFSDM control register 1
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CR1 DFSDM_FLT3CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.

0x1 : B_0x1

DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.

End of enumeration elements list.

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect.

0x1 : B_0x1

Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1.

End of enumeration elements list.

JSYNC : JSYNC
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch an injected conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger

End of enumeration elements list.

JSCAN : JSCAN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.

0x1 : B_0x1

The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.

End of enumeration elements list.

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read injected data

0x1 : B_0x1

The DMA channel is enabled to read injected data

End of enumeration elements list.

JEXTSEL : JEXTSEL
bits : 8 - 10 (3 bit)
access : read-write

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Trigger detection is disabled

0x1 : B_0x1

Each rising edge on the selected trigger makes a request to launch an injected conversion

0x2 : B_0x2

Each falling edge on the selected trigger makes a request to launch an injected conversion

0x3 : B_0x3

Both rising edges and falling edges on the selected trigger make requests to launch injected conversions

End of enumeration elements list.

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1.

End of enumeration elements list.

RCONT : RCONT
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The regular channel is converted just once for each conversion request

0x1 : B_0x1

The regular channel is converted repeatedly after each conversion request

End of enumeration elements list.

RSYNC : RSYNC
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Do not launch a regular conversion synchronously with DFSDM_FLT0

0x1 : B_0x1

Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0

End of enumeration elements list.

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The DMA channel is not enabled to read regular data

0x1 : B_0x1

The DMA channel is enabled to read regular data

End of enumeration elements list.

RCH : RCH
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel 0 is selected as the regular channel

0x1 : B_0x1

Channel 1 is selected as the regular channel

0x7 : B_0x7

Channel 7 is selected as the regular channel

End of enumeration elements list.

FAST : FAST
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Fast conversion mode disabled

0x1 : B_0x1

Fast conversion mode enabled

End of enumeration elements list.

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift

0x1 : B_0x1

Analog watchdog on channel transceivers value (after watchdog filter)

End of enumeration elements list.


DFSDM_FLT3CR2

DFSDM control register 2
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CR2 DFSDM_FLT3CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected end of conversion interrupt is disabled

0x1 : B_0x1

Injected end of conversion interrupt is enabled

End of enumeration elements list.

REOCIE : REOCIE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular end of conversion interrupt is disabled

0x1 : B_0x1

Regular end of conversion interrupt is enabled

End of enumeration elements list.

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Injected data overrun interrupt is disabled

0x1 : B_0x1

Injected data overrun interrupt is enabled

End of enumeration elements list.

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Regular data overrun interrupt is disabled

0x1 : B_0x1

Regular data overrun interrupt is enabled

End of enumeration elements list.

AWDIE : AWDIE
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Analog watchdog interrupt is disabled

0x1 : B_0x1

Analog watchdog interrupt is enabled

End of enumeration elements list.

SCDIE : SCDIE
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

short-circuit detector interrupt is disabled

0x1 : B_0x1

short-circuit detector interrupt is enabled

End of enumeration elements list.

CKABIE : CKABIE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Detection of channel input clock absence interrupt is disabled

0x1 : B_0x1

Detection of channel input clock absence interrupt is enabled

End of enumeration elements list.

EXCH : EXCH
bits : 8 - 15 (8 bit)
access : read-write

AWDCH : AWDCH
bits : 16 - 23 (8 bit)
access : read-write


DFSDM_FLT3ISR

DFSDM interrupt and status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3ISR DFSDM_FLT3ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion has completed

0x1 : B_0x1

An injected conversion has completed and its data may be read

End of enumeration elements list.

REOCF : REOCF
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion has completed

0x1 : B_0x1

A regular conversion has completed and its data may be read

End of enumeration elements list.

JOVRF : JOVRF
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No injected conversion overrun has occurred

0x1 : B_0x1

An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns

End of enumeration elements list.

ROVRF : ROVRF
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No regular conversion overrun has occurred

0x1 : B_0x1

A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns

End of enumeration elements list.

AWDF : AWDF
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No Analog watchdog event occurred

0x1 : B_0x1

The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.

End of enumeration elements list.

JCIP : JCIP
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the injected channel group (neither by software nor by trigger) has been issued

0x1 : B_0x1

The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection

End of enumeration elements list.

RCIP : RCIP
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No request to convert the regular channel has been issued

0x1 : B_0x1

The conversion of the regular channel is in progress or a request for a regular conversion is pending

End of enumeration elements list.

CKABF : CKABF
bits : 16 - 23 (8 bit)
access : read-only

SCDF : SCDF
bits : 24 - 31 (8 bit)
access : read-only


DFSDM_FLT3ICR

DFSDM interrupt flag clear register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3ICR DFSDM_FLT3ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Writing 0 has no effect

0x1 : B_0x1

Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register

End of enumeration elements list.

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
access : read-write

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
access : read-write


DFSDM_FLT3JCHGR

DFSDM injected channel group selection register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3JCHGR DFSDM_FLT3JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)
access : read-write


DFSDM_FLT3FCR

DFSDM filter control register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3FCR DFSDM_FLT3FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)
access : read-write

FOSR : FOSR
bits : 16 - 25 (10 bit)
access : read-write

FORD : FORD
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

0x4 : B_0x4

Sinc4 filter type

0x5 : B_0x5

Sinc5 filter type

End of enumeration elements list.


DFSDM_FLT3JDATAR

DFSDM data register for injected group
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3JDATAR DFSDM_FLT3JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)
access : read-only

JDATA : JDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT3RDATAR

DFSDM data register for the regular channel
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3RDATAR DFSDM_FLT3RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)
access : read-only

RPEND : RPEND
bits : 4 - 4 (1 bit)
access : read-only

RDATA : RDATA
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT3AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWHTR DFSDM_FLT3AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)
access : read-write

AWHT : AWHT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT3AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWLTR DFSDM_FLT3AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)
access : read-write

AWLT : AWLT
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT3AWSR

DFSDM analog watchdog status register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWSR DFSDM_FLT3AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)
access : read-only

AWHTF : AWHTF
bits : 8 - 15 (8 bit)
access : read-only


DFSDM_FLT3AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWCFR DFSDM_FLT3AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
access : read-write

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
access : read-write


DFSDM_FLT3EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3EXMAX DFSDM_FLT3EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
access : read-only

EXMAX : EXMAX
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT3EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3EXMIN DFSDM_FLT3EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-only


DFSDM_FLT3CNVTIMR

DFSDM conversion timer register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CNVTIMR DFSDM_FLT3CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
access : read-only


DFSDM_CH1WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1WDATR DFSDM_CH1WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH1DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1DATINR DFSDM_CH1DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_CH0CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0CFGR2 DFSDM_CH0CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH2CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2CFGR1 DFSDM_CH2CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH2CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2CFGR2 DFSDM_CH2CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH2AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2AWSCDR DFSDM_CH2AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH2WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2WDATR DFSDM_CH2WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH2DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2DATINR DFSDM_CH2DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_CH3CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3CFGR1 DFSDM_CH3CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH3CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3CFGR2 DFSDM_CH3CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH3AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3AWSCDR DFSDM_CH3AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH3WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3WDATR DFSDM_CH3WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH3DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3DATINR DFSDM_CH3DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_CH0AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0AWSCDR DFSDM_CH0AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH4CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4CFGR1 DFSDM_CH4CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH4CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4CFGR2 DFSDM_CH4CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH4AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4AWSCDR DFSDM_CH4AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH4WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4WDATR DFSDM_CH4WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH4DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4DATINR DFSDM_CH4DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_CH5CFGR1

This register specifies the parameters used by channel y.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5CFGR1 DFSDM_CH5CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH5CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5CFGR2 DFSDM_CH5CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH5AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5AWSCDR DFSDM_CH5AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH5WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5WDATR DFSDM_CH5WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH5DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5DATINR DFSDM_CH5DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_CH0WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0WDATR DFSDM_CH0WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH6CFGR1

This register specifies the parameters used by channel y.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6CFGR1 DFSDM_CH6CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH6CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6CFGR2 DFSDM_CH6CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH6AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6AWSCDR DFSDM_CH6AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH6WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6WDATR DFSDM_CH6WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH6DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6DATINR DFSDM_CH6DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write


DFSDM_CH7CFGR1

This register specifies the parameters used by channel y.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7CFGR1 DFSDM_CH7CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

SPI with rising edge to strobe data

0x1 : B_0x1

SPI with falling edge to strobe data

0x2 : B_0x2

Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

0x3 : B_0x3

Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

End of enumeration elements list.

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

clock coming from external CKINy input - sampling point according SITP[1:0]

0x1 : B_0x1

clock coming from internal CKOUT output - sampling point according SITP[1:0]

0x2 : B_0x2

clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.

0x3 : B_0x3

clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.

End of enumeration elements list.

SCDEN : SCDEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Input channel y will not be guarded by the short-circuit detector

0x1 : B_0x1

Input channel y will be continuously guarded by the short-circuit detector

End of enumeration elements list.

CKABEN : CKABEN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Clock absence detector disabled on channel y

0x1 : B_0x1

Clock absence detector enabled on channel y

End of enumeration elements list.

CHEN : CHEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel y disabled

0x1 : B_0x1

Channel y enabled

End of enumeration elements list.

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Channel inputs are taken from pins of the same channel y.

0x1 : B_0x1

Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

End of enumeration elements list.

DATMPX : DATMPX
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

0x1 : B_0x1

Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

0x2 : B_0x2

Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.

End of enumeration elements list.

DATPACK : DATPACK
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

0x1 : B_0x1

Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

0x2 : B_0x2

Dual: input data in DFSDM_CHyDATINR register are stored as two samples:

End of enumeration elements list.

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Output clock generation is disabled (CKOUT signal is set to low state)

End of enumeration elements list.

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Source for output clock is from system clock

0x1 : B_0x1

Source for output clock is from audio clock

End of enumeration elements list.

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DFSDM interface disabled

0x1 : B_0x1

DFSDM interface enabled

End of enumeration elements list.


DFSDM_CH7CFGR2

This register specifies the parameters used by channel y (y = 0..7).
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7CFGR2 DFSDM_CH7CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)
access : read-write

OFFSET : OFFSET
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_CH7AWSCDR

Short-circuit detector and analog watchdog settings for channel y (y = 0..7)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7AWSCDR DFSDM_CH7AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)
access : read-write

BKSCD : BKSCD
bits : 12 - 15 (4 bit)
access : read-write

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
access : read-write

AWFORD : AWFORD
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FastSinc filter type

0x1 : B_0x1

Sinc1 filter type

0x2 : B_0x2

Sinc2 filter type

0x3 : B_0x3

Sinc3 filter type

End of enumeration elements list.


DFSDM_CH7WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7).
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7WDATR DFSDM_CH7WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)
access : read-only


DFSDM_CH7DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7DATINR DFSDM_CH7DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
access : read-write

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
access : read-write



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