\n

DMAMUX1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DMAMUX1_C0CR (C0CR)

DMAMUX1_C4CR (C4CR)

DMAMUX1_RG0CR (RG0CR)

DMAMUX1_RG1CR (RG1CR)

DMAMUX1_RG2CR (RG2CR)

DMAMUX1_RG3CR (RG3CR)

DMAMUX1_RG4CR (RG4CR)

DMAMUX1_RG5CR (RG5CR)

DMAMUX1_RG6CR (RG6CR)

DMAMUX1_RG7CR (RG7CR)

DMAMUX1_C5CR (C5CR)

DMAMUX1_RGSR (RGSR)

DMAMUX1_RGCFR (RGCFR)

DMAMUX1_C6CR (C6CR)

DMAMUX1_C7CR (C7CR)

DMAMUX1_C8CR (C8CR)

DMAMUX1_C9CR (C9CR)

DMAMUX1_C10CR (C10CR)

DMAMUX1_C11CR (C11CR)

DMAMUX1_C12CR (C12CR)

DMAMUX1_C13CR (C13CR)

DMAMUX1_C14CR (C14CR)

DMAMUX1_C15CR (C15CR)

DMAMUX_HWCFGR2 (HWCFGR2)

DMAMUX_HWCFGR1 (HWCFGR1)

DMAMUX_VERR (VERR)

DMAMUX_IPIDR (IPIDR)

DMAMUX_SIDR (SIDR)

DMAMUX1_C1CR (C1CR)

DMAMUX1_C2CR (C2CR)

DMAMUX1_CSR (CSR)

DMAMUX1_CFR (CFR)

DMAMUX1_C3CR (C3CR)


DMAMUX1_C0CR (C0CR)

DMAMUX1 request line multiplexer channel 0 configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C0CR DMAMUX1_C0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C4CR (C4CR)

DMAMUX1 request line multiplexer channel 4 configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C4CR DMAMUX1_C4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_RG0CR (RG0CR)

DMAMUX1 request generator channel 0 configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG0CR DMAMUX1_RG0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG1CR (RG1CR)

DMAMUX1 request generator channel 1 configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG1CR DMAMUX1_RG1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG2CR (RG2CR)

DMAMUX1 request generator channel 2 configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG2CR DMAMUX1_RG2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG3CR (RG3CR)

DMAMUX1 request generator channel 3 configuration register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG3CR DMAMUX1_RG3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG4CR (RG4CR)

DMAMUX1 request generator channel 4 configuration register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG4CR DMAMUX1_RG4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG5CR (RG5CR)

DMAMUX1 request generator channel 5 configuration register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG5CR DMAMUX1_RG5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG6CR (RG6CR)

DMAMUX1 request generator channel 6 configuration register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG6CR DMAMUX1_RG6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_RG7CR (RG7CR)

DMAMUX1 request generator channel 7 configuration register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RG7CR DMAMUX1_RG7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write

OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt on a trigger overrun event occurrence is disabled

0x1 : B_0x1

interrupt on a trigger overrun event occurrence is enabled

End of enumeration elements list.

GE : GE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

DMA request generator channel x disabled

0x1 : B_0x1

DMA request generator channel x enabled

End of enumeration elements list.

GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. none trigger detection nor generation.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write


DMAMUX1_C5CR (C5CR)

DMAMUX1 request line multiplexer channel 5 configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C5CR DMAMUX1_C5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_RGSR (RGSR)

DMAMUX1 request generator interrupt status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RGSR DMAMUX1_RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF0 OF1 OF2 OF3 OF4 OF5 OF6 OF7

OF0 : OF0
bits : 0 - 0 (1 bit)
access : read-only

OF1 : OF1
bits : 1 - 1 (1 bit)
access : read-only

OF2 : OF2
bits : 2 - 2 (1 bit)
access : read-only

OF3 : OF3
bits : 3 - 3 (1 bit)
access : read-only

OF4 : OF4
bits : 4 - 4 (1 bit)
access : read-only

OF5 : OF5
bits : 5 - 5 (1 bit)
access : read-only

OF6 : OF6
bits : 6 - 6 (1 bit)
access : read-only

OF7 : OF7
bits : 7 - 7 (1 bit)
access : read-only


DMAMUX1_RGCFR (RGCFR)

DMAMUX1 request generator interrupt clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_RGCFR DMAMUX1_RGCFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COF0 COF1 COF2 COF3 COF4 COF5 COF6 COF7

COF0 : COF0
bits : 0 - 0 (1 bit)
access : read-only

COF1 : COF1
bits : 1 - 1 (1 bit)
access : read-only

COF2 : COF2
bits : 2 - 2 (1 bit)
access : read-only

COF3 : COF3
bits : 3 - 3 (1 bit)
access : read-only

COF4 : COF4
bits : 4 - 4 (1 bit)
access : read-only

COF5 : COF5
bits : 5 - 5 (1 bit)
access : read-only

COF6 : COF6
bits : 6 - 6 (1 bit)
access : read-only

COF7 : COF7
bits : 7 - 7 (1 bit)
access : read-only


DMAMUX1_C6CR (C6CR)

DMAMUX1 request line multiplexer channel 6 configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C6CR DMAMUX1_C6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C7CR (C7CR)

DMAMUX1 request line multiplexer channel 7 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C7CR DMAMUX1_C7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C8CR (C8CR)

DMAMUX1 request line multiplexer channel 8 configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C8CR DMAMUX1_C8CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C9CR (C9CR)

DMAMUX1 request line multiplexer channel 9 configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C9CR DMAMUX1_C9CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C10CR (C10CR)

DMAMUX1 request line multiplexer channel 10 configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C10CR DMAMUX1_C10CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C11CR (C11CR)

DMAMUX1 request line multiplexer channel 11 configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C11CR DMAMUX1_C11CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C12CR (C12CR)

DMAMUX1 request line multiplexer channel 12 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C12CR DMAMUX1_C12CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C13CR (C13CR)

DMAMUX1 request line multiplexer channel 13 configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C13CR DMAMUX1_C13CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C14CR (C14CR)

DMAMUX1 request line multiplexer channel 14 configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C14CR DMAMUX1_C14CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C15CR (C15CR)

DMAMUX1 request line multiplexer channel 15 configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C15CR DMAMUX1_C15CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX_HWCFGR2 (HWCFGR2)

DMAMUX hardware configuration 2 register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_HWCFGR2 DMAMUX_HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_DMA_EXT_REQ

NUM_DMA_EXT_REQ : NUM_DMA_EXT_REQ
bits : 0 - 7 (8 bit)


DMAMUX_HWCFGR1 (HWCFGR1)

DMAMUX hardware configuration 1 register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_HWCFGR1 DMAMUX_HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_DMA_STREAMS NUM_DMA_PERIPH_REQ NUM_DMA_TRIG NUM_DMA_REQGEN

NUM_DMA_STREAMS : NUM_DMA_STREAMS
bits : 0 - 7 (8 bit)

NUM_DMA_PERIPH_REQ : NUM_DMA_PERIPH_REQ
bits : 8 - 15 (8 bit)

NUM_DMA_TRIG : NUM_DMA_TRIG
bits : 16 - 23 (8 bit)

NUM_DMA_REQGEN : NUM_DMA_REQGEN
bits : 24 - 31 (8 bit)


DMAMUX_VERR (VERR)

DMAMUX IP Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_VERR DMAMUX_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


DMAMUX_IPIDR (IPIDR)

DMAMUX IP Version Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_IPIDR DMAMUX_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


DMAMUX_SIDR (SIDR)

DMAMUX IP Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_SIDR DMAMUX_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


DMAMUX1_C1CR (C1CR)

DMAMUX1 request line multiplexer channel 1 configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C1CR DMAMUX1_C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_C2CR (C2CR)

DMAMUX1 request line multiplexer channel 2 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C2CR DMAMUX1_C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write


DMAMUX1_CSR (CSR)

DMAMUX1 request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_CSR DMAMUX1_CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF0 SOF1 SOF2 SOF3 SOF4 SOF5 SOF6 SOF7 SOF8 SOF9 SOF10 SOF11 SOF12 SOF13 SOF14 SOF15

SOF0 : SOF0
bits : 0 - 0 (1 bit)
access : read-only

SOF1 : SOF1
bits : 1 - 1 (1 bit)
access : read-only

SOF2 : SOF2
bits : 2 - 2 (1 bit)
access : read-only

SOF3 : SOF3
bits : 3 - 3 (1 bit)
access : read-only

SOF4 : SOF4
bits : 4 - 4 (1 bit)
access : read-only

SOF5 : SOF5
bits : 5 - 5 (1 bit)
access : read-only

SOF6 : SOF6
bits : 6 - 6 (1 bit)
access : read-only

SOF7 : SOF7
bits : 7 - 7 (1 bit)
access : read-only

SOF8 : SOF8
bits : 8 - 8 (1 bit)
access : read-only

SOF9 : SOF9
bits : 9 - 9 (1 bit)
access : read-only

SOF10 : SOF10
bits : 10 - 10 (1 bit)
access : read-only

SOF11 : SOF11
bits : 11 - 11 (1 bit)
access : read-only

SOF12 : SOF12
bits : 12 - 12 (1 bit)
access : read-only

SOF13 : SOF13
bits : 13 - 13 (1 bit)
access : read-only

SOF14 : SOF14
bits : 14 - 14 (1 bit)
access : read-only

SOF15 : SOF15
bits : 15 - 15 (1 bit)
access : read-only


DMAMUX1_CFR (CFR)

DMAMUX1 request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_CFR DMAMUX1_CFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF0 CSOF1 CSOF2 CSOF3 CSOF4 CSOF5 CSOF6 CSOF7 CSOF8 CSOF9 CSOF10 CSOF11 CSOF12 CSOF13 CSOF14 CSOF15

CSOF0 : CSOF0
bits : 0 - 0 (1 bit)
access : write-only

CSOF1 : CSOF1
bits : 1 - 1 (1 bit)
access : write-only

CSOF2 : CSOF2
bits : 2 - 2 (1 bit)
access : write-only

CSOF3 : CSOF3
bits : 3 - 3 (1 bit)
access : write-only

CSOF4 : CSOF4
bits : 4 - 4 (1 bit)
access : write-only

CSOF5 : CSOF5
bits : 5 - 5 (1 bit)
access : write-only

CSOF6 : CSOF6
bits : 6 - 6 (1 bit)
access : write-only

CSOF7 : CSOF7
bits : 7 - 7 (1 bit)
access : write-only

CSOF8 : CSOF8
bits : 8 - 8 (1 bit)
access : write-only

CSOF9 : CSOF9
bits : 9 - 9 (1 bit)
access : write-only

CSOF10 : CSOF10
bits : 10 - 10 (1 bit)
access : write-only

CSOF11 : CSOF11
bits : 11 - 11 (1 bit)
access : write-only

CSOF12 : CSOF12
bits : 12 - 12 (1 bit)
access : write-only

CSOF13 : CSOF13
bits : 13 - 13 (1 bit)
access : write-only

CSOF14 : CSOF14
bits : 14 - 14 (1 bit)
access : write-only

CSOF15 : CSOF15
bits : 15 - 15 (1 bit)
access : write-only


DMAMUX1_C3CR (C3CR)

DMAMUX1 request line multiplexer channel 3 configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1_C3CR DMAMUX1_C3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write

SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

event generation disabled

0x1 : B_0x1

event generation enabled

End of enumeration elements list.

SE : SE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

synchronization disabled

0x1 : B_0x1

synchronization enabled

End of enumeration elements list.

SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no event. I.e. None synchronization nor detection.

0x1 : B_0x1

rising edge

0x2 : B_0x2

falling edge

0x3 : B_0x3

rising and falling edge

End of enumeration elements list.

NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.