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FDCAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FDCAN_CREL

FDCAN_TEST

FDCAN_TTTMC

FDCAN_TTRMC

FDCAN_TTOCF

FDCAN_TTMLM

FDCAN_TURCF

FDCAN_TTOCN

FDCAN_TTGTP

FDCAN_TTTMK

FDCAN_TTIR

FDCAN_TTIE

FDCAN_TTILS

FDCAN_TTOST

FDCAN_TURNA

FDCAN_TTLGT

FDCAN_TTCTC

FDCAN_TTCPT

FDCAN_RWD

FDCAN_TTCSM

FDCAN_CCCR

FDCAN_NBTP

FDCAN_TSCC

FDCAN_TSCV

FDCAN_TOCC

FDCAN_TOCV

FDCAN_TTTS

FDCAN_ENDN

FDCAN_ECR

FDCAN_PSR

FDCAN_TDCR

FDCAN_IR

FDCAN_IE

FDCAN_ILS

FDCAN_ILE

FDCAN_GFC

FDCAN_SIDFC

FDCAN_XIDFC

FDCAN_XIDAM

FDCAN_HPMS

FDCAN_NDAT1

FDCAN_NDAT2

FDCAN_RXF0C

FDCAN_RXF0S

FDCAN_RXF0A

FDCAN_RXBC

FDCAN_RXF1C

FDCAN_RXF1S

FDCAN_RXF1A

FDCAN_RXESC

FDCAN_DBTP

FDCAN_TXBC

FDCAN_TXFQS

FDCAN_TXESC

FDCAN_TXBRP

FDCAN_TXBAR

FDCAN_TXBCR

FDCAN_TXBTO

FDCAN_TXBCF

FDCAN_TXBTIE

FDCAN_TXBCIE

FDCAN_TXEFC

FDCAN_TXEFS

FDCAN_TXEFA


FDCAN_CREL

FDCAN Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_CREL FDCAN_CREL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY MON YEAR SUBSTEP STEP REL

DAY : DAY
bits : 0 - 7 (8 bit)
access : read-only

MON : MON
bits : 8 - 15 (8 bit)
access : read-only

YEAR : YEAR
bits : 16 - 19 (4 bit)
access : read-only

SUBSTEP : SUBSTEP
bits : 20 - 23 (4 bit)
access : read-only

STEP : STEP
bits : 24 - 27 (4 bit)
access : read-only

REL : REL
bits : 28 - 31 (4 bit)
access : read-only


FDCAN_TEST

Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TEST FDCAN_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBCK TX RX

LBCK : LBCK
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Reset value, Loop Back mode is disabled

0x1 : B_0x1

Loop Back mode is enabled (see Test modes)

End of enumeration elements list.

TX : TX
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time

0x1 : B_0x1

Sample point can be monitored at pin FDCANx_TX

0x2 : B_0x2

Dominant ( 0 ) level at pin FDCANx_TX

0x3 : B_0x3

Recessive ( 1 ) at pin FDCANx_TX

End of enumeration elements list.

RX : RX
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The CAN bus is dominant (FDCANx_RX = 0 )

0x1 : B_0x1

The CAN bus is recessive (FDCANx_RX = 1 )

End of enumeration elements list.


FDCAN_TTTMC

FDCAN TT trigger memory configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTTMC FDCAN_TTTMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMSA TME

TMSA : TMSA
bits : 2 - 15 (14 bit)
access : read-write

TME : TME
bits : 16 - 22 (7 bit)
access : read-write


FDCAN_TTRMC

FDCAN TT reference message configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTRMC FDCAN_TTRMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RID XTD RMPS

RID : RID
bits : 0 - 28 (29 bit)
access : read-write

XTD : XTD
bits : 30 - 30 (1 bit)
access : read-write

RMPS : RMPS
bits : 31 - 31 (1 bit)
access : read-write


FDCAN_TTOCF

FDCAN TT operation configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTOCF FDCAN_TTOCF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OM GEN TM LDSDL IRTO EECS AWL EGTF ECC EVTP

OM : OM
bits : 0 - 1 (2 bit)
access : read-write

GEN : GEN
bits : 3 - 3 (1 bit)
access : read-write

TM : TM
bits : 4 - 4 (1 bit)
access : read-write

LDSDL : LDSDL
bits : 5 - 7 (3 bit)
access : read-write

IRTO : IRTO
bits : 8 - 14 (7 bit)
access : read-write

EECS : EECS
bits : 15 - 15 (1 bit)
access : read-write

AWL : AWL
bits : 16 - 23 (8 bit)
access : read-write

EGTF : EGTF
bits : 24 - 24 (1 bit)
access : read-write

ECC : ECC
bits : 25 - 25 (1 bit)
access : read-write

EVTP : EVTP
bits : 26 - 26 (1 bit)
access : read-write


FDCAN_TTMLM

FDCAN TT matrix limits register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTMLM FDCAN_TTMLM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCM CSS TXEW ENTT

CCM : CCM
bits : 0 - 5 (6 bit)
access : read-write

CSS : CSS
bits : 6 - 7 (2 bit)
access : read-write

TXEW : TXEW
bits : 8 - 11 (4 bit)
access : read-write

ENTT : ENTT
bits : 16 - 27 (12 bit)
access : read-write


FDCAN_TURCF

FDCAN TUR configuration register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TURCF FDCAN_TURCF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCL DC ELT

NCL : NCL
bits : 0 - 15 (16 bit)
access : read-write

DC : DC
bits : 16 - 30 (15 bit)
access : read-write

ELT : ELT
bits : 31 - 31 (1 bit)
access : read-write


FDCAN_TTOCN

FDCAN TT operation control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTOCN FDCAN_TTOCN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGT ECS SWP SWS RTIE TMC TTIE GCS FGP TMG NIG ESCN LCKC

SGT : SGT
bits : 0 - 0 (1 bit)
access : read-write

ECS : ECS
bits : 1 - 1 (1 bit)
access : read-write

SWP : SWP
bits : 2 - 2 (1 bit)
access : read-write

SWS : SWS
bits : 3 - 4 (2 bit)
access : read-write

RTIE : RTIE
bits : 5 - 5 (1 bit)
access : read-write

TMC : TMC
bits : 6 - 7 (2 bit)
access : read-write

TTIE : TTIE
bits : 8 - 8 (1 bit)
access : read-write

GCS : GCS
bits : 9 - 9 (1 bit)
access : read-write

FGP : FGP
bits : 10 - 10 (1 bit)
access : read-write

TMG : TMG
bits : 11 - 11 (1 bit)
access : read-write

NIG : NIG
bits : 12 - 12 (1 bit)
access : read-write

ESCN : ESCN
bits : 13 - 13 (1 bit)
access : read-write

LCKC : LCKC
bits : 15 - 15 (1 bit)
access : read-write


FDCAN_TTGTP

FDCAN TT global time preset register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTGTP FDCAN_TTGTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TP CTP

TP : TP
bits : 0 - 15 (16 bit)
access : read-write

CTP : CTP
bits : 16 - 31 (16 bit)
access : read-write


FDCAN_TTTMK

FDCAN TT time mark register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTTMK FDCAN_TTTMK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TM TICC LCKM

TM : TM
bits : 0 - 15 (16 bit)
access : read-write

TICC : TICC
bits : 16 - 22 (7 bit)
access : read-write

LCKM : LCKM
bits : 31 - 31 (1 bit)
access : read-only


FDCAN_TTIR

FDCAN TT Interrupt register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTIR FDCAN_TTIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBC SMC CSM SOG RTMI TTMI SWE GTW GTD GTE TXU TXO SE1 SE2 ELC IWTG WT AW CER

SBC : SBC
bits : 0 - 0 (1 bit)
access : read-write

SMC : SMC
bits : 1 - 1 (1 bit)
access : read-write

CSM : CSM
bits : 2 - 2 (1 bit)
access : read-write

SOG : SOG
bits : 3 - 3 (1 bit)
access : read-write

RTMI : RTMI
bits : 4 - 4 (1 bit)
access : read-write

TTMI : TTMI
bits : 5 - 5 (1 bit)
access : read-write

SWE : SWE
bits : 6 - 6 (1 bit)
access : read-write

GTW : GTW
bits : 7 - 7 (1 bit)
access : read-write

GTD : GTD
bits : 8 - 8 (1 bit)
access : read-write

GTE : GTE
bits : 9 - 9 (1 bit)
access : read-write

TXU : TXU
bits : 10 - 10 (1 bit)
access : read-write

TXO : TXO
bits : 11 - 11 (1 bit)
access : read-write

SE1 : SE1
bits : 12 - 12 (1 bit)
access : read-write

SE2 : SE2
bits : 13 - 13 (1 bit)
access : read-write

ELC : ELC
bits : 14 - 14 (1 bit)
access : read-write

IWTG : IWTG
bits : 15 - 15 (1 bit)
access : read-write

WT : WT
bits : 16 - 16 (1 bit)
access : read-write

AW : AW
bits : 17 - 17 (1 bit)
access : read-write

CER : CER
bits : 18 - 18 (1 bit)
access : read-write


FDCAN_TTIE

FDCAN TT interrupt enable register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTIE FDCAN_TTIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBCE SMCE CSME SOGE RTMIE TTMIE SWEE GTWE GTDE GTEE TXUE TXOE SE1E SE2E ELCE IWTGE WTE AWE CERE

SBCE : SBCE
bits : 0 - 0 (1 bit)
access : read-write

SMCE : SMCE
bits : 1 - 1 (1 bit)
access : read-write

CSME : CSME
bits : 2 - 2 (1 bit)
access : read-write

SOGE : SOGE
bits : 3 - 3 (1 bit)
access : read-write

RTMIE : RTMIE
bits : 4 - 4 (1 bit)
access : read-write

TTMIE : TTMIE
bits : 5 - 5 (1 bit)
access : read-write

SWEE : SWEE
bits : 6 - 6 (1 bit)
access : read-write

GTWE : GTWE
bits : 7 - 7 (1 bit)
access : read-write

GTDE : GTDE
bits : 8 - 8 (1 bit)
access : read-write

GTEE : GTEE
bits : 9 - 9 (1 bit)
access : read-write

TXUE : TXUE
bits : 10 - 10 (1 bit)
access : read-write

TXOE : TXOE
bits : 11 - 11 (1 bit)
access : read-write

SE1E : SE1E
bits : 12 - 12 (1 bit)
access : read-write

SE2E : SE2E
bits : 13 - 13 (1 bit)
access : read-write

ELCE : ELCE
bits : 14 - 14 (1 bit)
access : read-write

IWTGE : IWTGE
bits : 15 - 15 (1 bit)
access : read-write

WTE : WTE
bits : 16 - 16 (1 bit)
access : read-write

AWE : AWE
bits : 17 - 17 (1 bit)
access : read-write

CERE : CERE
bits : 18 - 18 (1 bit)
access : read-write


FDCAN_TTILS

FDCAN TT interrupt line select register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTILS FDCAN_TTILS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBCL SMCL CSML SOGL RTMIL TTMIL SWEL GTWL GTDL GTEL TXUL TXOL SE1L SE2L ELCL IWTGL WTL AWL CERL

SBCL : SBCL
bits : 0 - 0 (1 bit)
access : read-write

SMCL : SMCL
bits : 1 - 1 (1 bit)
access : read-write

CSML : CSML
bits : 2 - 2 (1 bit)
access : read-write

SOGL : SOGL
bits : 3 - 3 (1 bit)
access : read-write

RTMIL : RTMIL
bits : 4 - 4 (1 bit)
access : read-write

TTMIL : TTMIL
bits : 5 - 5 (1 bit)
access : read-write

SWEL : SWEL
bits : 6 - 6 (1 bit)
access : read-write

GTWL : GTWL
bits : 7 - 7 (1 bit)
access : read-write

GTDL : GTDL
bits : 8 - 8 (1 bit)
access : read-write

GTEL : GTEL
bits : 9 - 9 (1 bit)
access : read-write

TXUL : TXUL
bits : 10 - 10 (1 bit)
access : read-write

TXOL : TXOL
bits : 11 - 11 (1 bit)
access : read-write

SE1L : SE1L
bits : 12 - 12 (1 bit)
access : read-write

SE2L : SE2L
bits : 13 - 13 (1 bit)
access : read-write

ELCL : ELCL
bits : 14 - 14 (1 bit)
access : read-write

IWTGL : IWTGL
bits : 15 - 15 (1 bit)
access : read-write

WTL : WTL
bits : 16 - 16 (1 bit)
access : read-write

AWL : AWL
bits : 17 - 17 (1 bit)
access : read-write

CERL : CERL
bits : 18 - 18 (1 bit)
access : read-write


FDCAN_TTOST

FDCAN TT Operation Status Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTOST FDCAN_TTOST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EL MS SYS GTP QCS RTO WGTD GFI TMP GSI WFE AWE WECS SPL

EL : Error Level
bits : 0 - 1 (2 bit)

MS : Master State.
bits : 2 - 3 (2 bit)

SYS : Synchronization State
bits : 4 - 5 (2 bit)

GTP : Quality of Global Time Phase
bits : 6 - 6 (1 bit)

QCS : Quality of Clock Speed
bits : 7 - 7 (1 bit)

RTO : Reference Trigger Offset
bits : 8 - 15 (8 bit)

WGTD : Wait for Global Time Discontinuity
bits : 22 - 22 (1 bit)

GFI : Gap Finished Indicator.
bits : 23 - 23 (1 bit)

TMP : Time Master Priority
bits : 24 - 26 (3 bit)

GSI : Gap Started Indicator.
bits : 27 - 27 (1 bit)

WFE : Wait for Event
bits : 28 - 28 (1 bit)

AWE : Application Watchdog Event
bits : 29 - 29 (1 bit)

WECS : Wait for External Clock Synchronization
bits : 30 - 30 (1 bit)

SPL : Schedule Phase Lock
bits : 31 - 31 (1 bit)


FDCAN_TURNA

FDCAN TUR Numerator Actual Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TURNA FDCAN_TURNA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NAV

NAV : Numerator Actual Value
bits : 0 - 17 (18 bit)


FDCAN_TTLGT

FDCAN TT Local and Global Time Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTLGT FDCAN_TTLGT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT GT

LT : Local Time
bits : 0 - 15 (16 bit)

GT : Global Time
bits : 16 - 31 (16 bit)


FDCAN_TTCTC

FDCAN TT Cycle Time and Count Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTCTC FDCAN_TTCTC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CT CC

CT : Cycle Time
bits : 0 - 15 (16 bit)

CC : Cycle Count
bits : 16 - 21 (6 bit)


FDCAN_TTCPT

FDCAN TT Capture Time Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTCPT FDCAN_TTCPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CT SWV

CT : Cycle Count Value
bits : 0 - 5 (6 bit)

SWV : Stop Watch Value
bits : 16 - 31 (16 bit)


FDCAN_RWD

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RWD FDCAN_RWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDC WDV

WDC : WDC
bits : 0 - 7 (8 bit)
access : read-write

WDV : WDV
bits : 8 - 15 (8 bit)
access : read-only


FDCAN_TTCSM

FDCAN TT Cycle Sync Mark Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTCSM FDCAN_TTCSM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSM

CSM : Cycle Sync Mark
bits : 0 - 15 (16 bit)


FDCAN_CCCR

For details about setting and resetting of single bits see Software initialization.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_CCCR FDCAN_CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT CCE ASM CSA CSR MON DAR TEST FDOE BRSE PXHD EFBI TXP NISO

INIT : INIT
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Normal Operation

0x1 : B_0x1

Initialization is started

End of enumeration elements list.

CCE : CCE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The CPU has no write access to the protected configuration registers

0x1 : B_0x1

The CPU has write access to the protected configuration registers (while CCCR.INIT = 1 )

End of enumeration elements list.

ASM : ASM
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Normal CAN operation

0x1 : B_0x1

Restricted Operation Mode active

End of enumeration elements list.

CSA : CSA
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No clock stop acknowledged

0x1 : B_0x1

FDCAN may be set in power down by stopping APB clock and kernel clock

End of enumeration elements list.

CSR : CSR
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No clock stop is requested

0x1 : B_0x1

Clock stop requested. When clock stop is requested, first INIT and then CSA will be set

End of enumeration elements list.

MON : MON
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Bus Monitoring Mode is disabled

0x1 : B_0x1

Bus Monitoring Mode is enabled

End of enumeration elements list.

DAR : DAR
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Automatic retransmission of messages not transmitted successfully enabled

0x1 : B_0x1

Automatic retransmission disabled

End of enumeration elements list.

TEST : TEST
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Normal operation, register TEST holds reset values

0x1 : B_0x1

Test Mode, write access to register TEST enabled

End of enumeration elements list.

FDOE : FDOE
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

FD operation disabled

0x1 : B_0x1

FD operation enabled

End of enumeration elements list.

BRSE : BRSE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Bit rate switching for transmissions disabled

0x1 : B_0x1

Bit rate switching for transmissions enabled

End of enumeration elements list.

PXHD : PXHD
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Protocol exception handling enabled

0x1 : B_0x1

Protocol exception handling disabled

End of enumeration elements list.

EFBI : EFBI
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Edge filtering disabled

0x1 : B_0x1

Two consecutive dominant tq required to detect an edge for hard synchronization

End of enumeration elements list.

TXP : TXP
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

disabled

0x1 : B_0x1

enabled

End of enumeration elements list.

NISO : NISO
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

CAN FD frame format according to ISO11898-1

0x1 : B_0x1

CAN FD frame format according to Bosch CAN FD Specification V1.0

End of enumeration elements list.


FDCAN_NBTP

FDCAN_NBTP
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_NBTP FDCAN_NBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEG2 NTSEG1 NBRP NSJW

TSEG2 : TSEG2
bits : 0 - 6 (7 bit)
access : read-write

NTSEG1 : NTSEG1
bits : 8 - 15 (8 bit)
access : read-write

NBRP : NBRP
bits : 16 - 24 (9 bit)
access : read-write

NSJW : NSJW
bits : 25 - 31 (7 bit)
access : read-write


FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TSCC FDCAN_TSCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS TCP

TSS : TSS
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Timestamp counter value always 0x0000

0x1 : B_0x1

Timestamp counter value incremented according to TCP

0x2 : B_0x2

External timestamp counter from TIM3 value used (tim3_cnt[0:15])

0x3 : B_0x3

Same as 00 .

End of enumeration elements list.

TCP : TCP
bits : 16 - 19 (4 bit)
access : read-write


FDCAN_TSCV

FDCAN Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TSCV FDCAN_TSCV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC

TSC : TSC
bits : 0 - 15 (16 bit)
access : read-only


FDCAN_TOCC

FDCAN Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TOCC FDCAN_TOCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETOC TOS TOP

ETOC : ETOC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Timeout Counter disabled

0x1 : B_0x1

Timeout Counter enabled

End of enumeration elements list.

TOS : TOS
bits : 1 - 2 (2 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Continuous operation

0x1 : B_0x1

Timeout controlled by Tx Event FIFO

0x2 : B_0x2

Timeout controlled by Rx FIFO 0

0x3 : B_0x3

Timeout controlled by Rx FIFO 1

End of enumeration elements list.

TOP : TOP
bits : 16 - 31 (16 bit)
access : read-write


FDCAN_TOCV

FDCAN Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TOCV FDCAN_TOCV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC

TOC : TOC
bits : 0 - 15 (16 bit)
access : read-only


FDCAN_TTTS

FDCAN TT Trigger Select Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TTTS FDCAN_TTTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTDEL EVTSEL

SWTDEL : Stop watch trigger input selection
bits : 0 - 1 (2 bit)

EVTSEL : Event trigger input selection
bits : 4 - 5 (2 bit)


FDCAN_ENDN

FDCAN Core Release Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ENDN FDCAN_ENDN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETV

ETV : ETV
bits : 0 - 31 (32 bit)
access : read-only


FDCAN_ECR

FDCAN Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ECR FDCAN_ECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC TREC RP CEL

TEC : TEC
bits : 0 - 7 (8 bit)
access : read-only

TREC : TREC
bits : 8 - 14 (7 bit)
access : read-only

RP : RP
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

The Receive Error Counter is below the error passive level of 128

0x1 : B_0x1

The Receive Error Counter has reached the error passive level of 128

End of enumeration elements list.

CEL : CEL
bits : 16 - 23 (8 bit)
access : read-only


FDCAN_PSR

FDCAN Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_PSR FDCAN_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC ACT EP EW BO DLEC RESI RBRS REDL PXE TDCV

LEC : LEC
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Error: No error occurred since LEC has been reset by successful reception or transmission.

0x1 : B_0x1

Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

0x2 : B_0x2

Form Error: A fixed format part of a received frame has the wrong format.

0x3 : B_0x3

AckError: The message transmitted by the FDCAN was not acknowledged by another node.

0x4 : B_0x4

Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1 ), but the monitored bus value was dominant.

0x5 : B_0x5

Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0 ), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

0x6 : B_0x6

CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.

0x7 : B_0x7

NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7 . When the LEC shows the value 7 , no CAN bus event was detected since the last CPU read access to the Protocol Status Register.

End of enumeration elements list.

ACT : ACT
bits : 3 - 4 (2 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Synchronizing: node is synchronizing on CAN communication

0x1 : B_0x1

Idle: node is neither receiver nor transmitter

0x2 : B_0x2

Receiver: node is operating as receiver

0x3 : B_0x3

Transmitter: node is operating as transmitter

End of enumeration elements list.

EP : EP
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected

0x1 : B_0x1

The FDCAN is in the Error_Passive state

End of enumeration elements list.

EW : EW
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Both error counters are below the Error_Warning limit of 96

0x1 : B_0x1

At least one of error counter has reached the Error_Warning limit of 96

End of enumeration elements list.

BO : BO
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

The FDCAN is not Bus_Off

0x1 : B_0x1

The FDCAN is in Bus_Off state

End of enumeration elements list.

DLEC : DLEC
bits : 8 - 10 (3 bit)
access : write-only

RESI : RESI
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Last received FDCAN message did not have its ESI flag set

0x1 : B_0x1

Last received FDCAN message had its ESI flag set

End of enumeration elements list.

RBRS : RBRS
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Last received FDCAN message did not ha ve its BRS flag set

0x1 : B_0x1

Last received FDCAN message had its BRS flag set

End of enumeration elements list.

REDL : REDL
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Since this bit was reset by the CPU, no FDCAN message has been received

0x1 : B_0x1

Message in FDCAN format with EDL flag set has been received

End of enumeration elements list.

PXE : PXE
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No protocol exception event occurred since last read access

0x1 : B_0x1

Protocol exception event occurred

End of enumeration elements list.

TDCV : TDCV
bits : 16 - 22 (7 bit)
access : read-write


FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TDCR FDCAN_TDCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCF TDCO

TDCF : TDCF
bits : 0 - 6 (7 bit)
access : read-only

TDCO : TDCO
bits : 8 - 14 (7 bit)
access : read-only


FDCAN_IR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_IR FDCAN_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0N RF0W RF0F RF0L RF1N RF1W RF1F RF1L HPM TC TCF TFE TEFN TEFW TEFF TEFL TSW MRAF TOO DRX ELO EP EW BO WDI PEA PED ARA

RF0N : RF0N
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No new message written to Rx FIFO 0

0x1 : B_0x1

New message written to Rx FIFO 0

End of enumeration elements list.

RF0W : RF0W
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Rx FIFO 0 fill level below watermark

0x1 : B_0x1

Rx FIFO 0 fill level reached watermark

End of enumeration elements list.

RF0F : RF0F
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Rx FIFO 0 not full

0x1 : B_0x1

Rx FIFO 0 full

End of enumeration elements list.

RF0L : RF0L
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Rx FIFO 0 message lost

0x1 : B_0x1

Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

End of enumeration elements list.

RF1N : RF1N
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No new message written to Rx FIFO 1

0x1 : B_0x1

New message written to Rx FIFO 1

End of enumeration elements list.

RF1W : RF1W
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Rx FIFO 1 fill level below watermark

0x1 : B_0x1

Rx FIFO 1 fill level reached watermark

End of enumeration elements list.

RF1F : RF1F
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Rx FIFO 1 not full

0x1 : B_0x1

Rx FIFO 1 full

End of enumeration elements list.

RF1L : RF1L
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Rx FIFO 1 message lost

0x1 : B_0x1

Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

End of enumeration elements list.

HPM : HPM
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No high priority message received

0x1 : B_0x1

High priority message received

End of enumeration elements list.

TC : TC
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No transmission completed

0x1 : B_0x1

Transmission completed

End of enumeration elements list.

TCF : TCF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No transmission cancellation finished

0x1 : B_0x1

Transmission cancellation finished

End of enumeration elements list.

TFE : TFE
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Tx FIFO non-empty

0x1 : B_0x1

Tx FIFO empty

End of enumeration elements list.

TEFN : TEFN
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Tx Event FIFO unchanged

0x1 : B_0x1

Tx Handler wrote Tx Event FIFO element

End of enumeration elements list.

TEFW : TEFW
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Tx Event FIFO fill level below watermark

0x1 : B_0x1

Tx Event FIFO fill level reached watermark

End of enumeration elements list.

TEFF : TEFF
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Tx Event FIFO not full

0x1 : B_0x1

Tx Event FIFO full

End of enumeration elements list.

TEFL : TEFL
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Tx Event FIFO element lost

0x1 : B_0x1

Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero

End of enumeration elements list.

TSW : TSW
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No timestamp counter wrap-around

0x1 : B_0x1

Timestamp counter wrapped around

End of enumeration elements list.

MRAF : MRAF
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Message RAM access failure occurred

0x1 : B_0x1

Message RAM access failure occurred

End of enumeration elements list.

TOO : TOO
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No timeout

0x1 : B_0x1

Timeout reached

End of enumeration elements list.

DRX : DRX
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No timeout

0x1 : B_0x1

Timeout reached

End of enumeration elements list.

ELO : ELO
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

CAN Error Logging Counter did not overflow

0x1 : B_0x1

Overflow of CAN Error Logging Counter occurred

End of enumeration elements list.

EP : EP
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Error_Passive status unchanged

0x1 : B_0x1

Error_Passive status changed

End of enumeration elements list.

EW : EW
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Error_Warning status unchanged

0x1 : B_0x1

Error_Warning status changed

End of enumeration elements list.

BO : BO
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Bus_Off status unchanged

0x1 : B_0x1

Bus_Off status changed

End of enumeration elements list.

WDI : WDI
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Message RAM Watchdog event occurred

0x1 : B_0x1

Message RAM Watchdog event due to missing READY

End of enumeration elements list.

PEA : PEA
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No protocol error in arbitration phase

0x1 : B_0x1

Protocol error in arbitration phase detected (PSR.LEC different from 0,7)

End of enumeration elements list.

PED : PED
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No protocol error in data phase

0x1 : B_0x1

Protocol error in data phase detected (PSR.DLEC different from 0,7)

End of enumeration elements list.

ARA : ARA
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No access to reserved address occurred

0x1 : B_0x1

Access to reserved address occurred

End of enumeration elements list.


FDCAN_IE

The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_IE FDCAN_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NE RF0WE RF0FE RF0LE RF1NE RF1WE RF1FE RF1LE HPME TCE TCFE TFEE TEFNE TEFWE TEFFE TEFLE TSWE MRAFE TOOE DRX BECE BEUE ELOE EPE EWE BOE WDIE PEAE PEDE ARAE

RF0NE : RF0NE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF0WE : RF0WE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF0FE : RF0FE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF0LE : RF0LE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF1NE : RF1NE
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF1WE : RF1WE
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF1FE : RF1FE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

RF1LE : RF1LE
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

HPME : HPME
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TCE : TCE
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TCFE : TCFE
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TFEE : TFEE
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TEFNE : TEFNE
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TEFWE : TEFWE
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TEFFE : TEFFE
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TEFLE : TEFLE
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TSWE : TSWE
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

MRAFE : MRAFE
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

TOOE : TOOE
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

DRX : DRX
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No timeout

0x1 : B_0x1

Timeout reached

End of enumeration elements list.

BECE : BECE
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

BEUE : BEUE
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

ELOE : ELOE
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

EPE : EPE
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

EWE : EWE
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

BOE : BOE
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

WDIE : WDIE
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt disabled

0x1 : B_0x1

Interrupt enabled

End of enumeration elements list.

PEAE : PEAE
bits : 27 - 27 (1 bit)
access : read-write

PEDE : PEDE
bits : 28 - 28 (1 bit)
access : read-write

ARAE : ARAE
bits : 29 - 29 (1 bit)
access : read-write


FDCAN_ILS

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ILS FDCAN_ILS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NL RF0WL RF0FL RF0LL RF1NL RF1WL RF1FL RF1LL HPML TCL TCFL TFEL TEFNL TEFWL TEFFL TEFLL TSWL MRAFL TOOL DRXL BECL BEUL ELOL EPL EWL BOL WDIL PEAL PEDL ARAL

RF0NL : RF0NL
bits : 0 - 0 (1 bit)
access : read-write

RF0WL : RF0WL
bits : 1 - 1 (1 bit)
access : read-write

RF0FL : RF0FL
bits : 2 - 2 (1 bit)
access : read-write

RF0LL : RF0LL
bits : 3 - 3 (1 bit)
access : read-write

RF1NL : RF1NL
bits : 4 - 4 (1 bit)
access : read-write

RF1WL : RF1WL
bits : 5 - 5 (1 bit)
access : read-write

RF1FL : RF1FL
bits : 6 - 6 (1 bit)
access : read-write

RF1LL : RF1LL
bits : 7 - 7 (1 bit)
access : read-write

HPML : HPML
bits : 8 - 8 (1 bit)
access : read-write

TCL : TCL
bits : 9 - 9 (1 bit)
access : read-write

TCFL : TCFL
bits : 10 - 10 (1 bit)
access : read-write

TFEL : TFEL
bits : 11 - 11 (1 bit)
access : read-write

TEFNL : TEFNL
bits : 12 - 12 (1 bit)
access : read-write

TEFWL : TEFWL
bits : 13 - 13 (1 bit)
access : read-write

TEFFL : TEFFL
bits : 14 - 14 (1 bit)
access : read-write

TEFLL : TEFLL
bits : 15 - 15 (1 bit)
access : read-write

TSWL : TSWL
bits : 16 - 16 (1 bit)
access : read-write

MRAFL : MRAFL
bits : 17 - 17 (1 bit)
access : read-write

TOOL : TOOL
bits : 18 - 18 (1 bit)
access : read-write

DRXL : DRXL
bits : 19 - 19 (1 bit)
access : read-write

BECL : BECL
bits : 20 - 20 (1 bit)
access : read-write

BEUL : BEUL
bits : 21 - 21 (1 bit)
access : read-write

ELOL : ELOL
bits : 22 - 22 (1 bit)
access : read-write

EPL : EPL
bits : 23 - 23 (1 bit)
access : read-write

EWL : EWL
bits : 24 - 24 (1 bit)
access : read-write

BOL : BOL
bits : 25 - 25 (1 bit)
access : read-write

WDIL : WDIL
bits : 26 - 26 (1 bit)
access : read-write

PEAL : PEAL
bits : 27 - 27 (1 bit)
access : read-write

PEDL : PEDL
bits : 28 - 28 (1 bit)
access : read-write

ARAL : ARAL
bits : 29 - 29 (1 bit)
access : read-write


FDCAN_ILE

Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ILE FDCAN_ILE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT0 EINT1

EINT0 : EINT0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt line fdcan_intr1_it disabled

0x1 : B_0x1

Interrupt line fdcan_intr1_it enabled

End of enumeration elements list.

EINT1 : EINT1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Interrupt line fdcan_intr0_it disabled

0x1 : B_0x1

Interrupt line fdcan_intr0_it enabled

End of enumeration elements list.


FDCAN_GFC

Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_GFC FDCAN_GFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRFE RRFS ANFE ANFS

RRFE : RRFE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Filter remote frames with 29-bit standard IDs

0x1 : B_0x1

Reject all remote frames with 29-bit standard IDs

End of enumeration elements list.

RRFS : RRFS
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Filter remote frames with 11-bit standard IDs

0x1 : B_0x1

Reject all remote frames with 11-bit standard IDs

End of enumeration elements list.

ANFE : ANFE
bits : 2 - 3 (2 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Accept in Rx FIFO 0

0x1 : B_0x1

Accept in Rx FIFO 1

0x2 : B_0x2

Reject

0x3 : B_0x3

Reject

End of enumeration elements list.

ANFS : ANFS
bits : 4 - 5 (2 bit)
access : write-only

Enumeration:

0x0 : B_0x0

Accept in Rx FIFO 0

0x1 : B_0x1

Accept in Rx FIFO 1

0x2 : B_0x2

Reject

0x3 : B_0x3

Reject

End of enumeration elements list.


FDCAN_SIDFC

Settings for 11-bit standard Message ID filtering.The Standard ID Filter Configuration controls the filter path for standard messages as described in Figure706: Standard Message ID filter path.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_SIDFC FDCAN_SIDFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLSSA LSS

FLSSA : FLSSA
bits : 2 - 15 (14 bit)
access : read-write

LSS : LSS
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No standard Message ID filter

End of enumeration elements list.


FDCAN_XIDFC

Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages as described in Figure707: Extended Message ID filter path.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_XIDFC FDCAN_XIDFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLESA LSE

FLESA : FLESA
bits : 2 - 15 (14 bit)
access : read-write

LSE : LSE
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No standard Message ID filter

End of enumeration elements list.


FDCAN_XIDAM

FDCAN Extended ID and Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_XIDAM FDCAN_XIDAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIDM

EIDM : EIDM
bits : 0 - 28 (29 bit)
access : read-write


FDCAN_HPMS

This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_HPMS FDCAN_HPMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIDX MSI FIDX FLST

BIDX : BIDX
bits : 0 - 5 (6 bit)
access : read-only

MSI : MSI
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No FIFO selected

0x1 : B_0x1

FIFO overrun

0x2 : B_0x2

Message stored in FIFO 0

0x3 : B_0x3

Message stored in FIFO 1

End of enumeration elements list.

FIDX : FIDX
bits : 8 - 14 (7 bit)
access : read-only

FLST : FLST
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

Standard Filter List

0x1 : B_0x1

Extended Filter List

End of enumeration elements list.


FDCAN_NDAT1

FDCAN new data 1 register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_NDAT1 FDCAN_NDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ND0 ND1 ND2 ND3 ND4 ND5 ND6 ND7 ND8 ND9 ND10 ND11 ND12 ND13 ND14 ND15 ND16 ND17 ND18 ND19 ND20 ND21 ND22 ND23 ND24 ND25 ND26 ND27 ND28 ND29 ND30 ND31

ND0 : ND0
bits : 0 - 0 (1 bit)

ND1 : ND1
bits : 1 - 1 (1 bit)

ND2 : ND2
bits : 2 - 2 (1 bit)

ND3 : ND3
bits : 3 - 3 (1 bit)

ND4 : ND4
bits : 4 - 4 (1 bit)

ND5 : ND5
bits : 5 - 5 (1 bit)

ND6 : ND6
bits : 6 - 6 (1 bit)

ND7 : ND7
bits : 7 - 7 (1 bit)

ND8 : ND8
bits : 8 - 8 (1 bit)

ND9 : ND9
bits : 9 - 9 (1 bit)

ND10 : ND10
bits : 10 - 10 (1 bit)

ND11 : ND11
bits : 11 - 11 (1 bit)

ND12 : ND12
bits : 12 - 12 (1 bit)

ND13 : ND13
bits : 13 - 13 (1 bit)

ND14 : ND14
bits : 14 - 14 (1 bit)

ND15 : ND15
bits : 15 - 15 (1 bit)

ND16 : ND16
bits : 16 - 16 (1 bit)

ND17 : ND17
bits : 17 - 17 (1 bit)

ND18 : ND18
bits : 18 - 18 (1 bit)

ND19 : ND19
bits : 19 - 19 (1 bit)

ND20 : ND20
bits : 20 - 20 (1 bit)

ND21 : ND21
bits : 21 - 21 (1 bit)

ND22 : ND22
bits : 22 - 22 (1 bit)

ND23 : ND23
bits : 23 - 23 (1 bit)

ND24 : ND24
bits : 24 - 24 (1 bit)

ND25 : ND25
bits : 25 - 25 (1 bit)

ND26 : ND26
bits : 26 - 26 (1 bit)

ND27 : ND27
bits : 27 - 27 (1 bit)

ND28 : ND28
bits : 28 - 28 (1 bit)

ND29 : ND29
bits : 29 - 29 (1 bit)

ND30 : ND30
bits : 30 - 30 (1 bit)

ND31 : ND31
bits : 31 - 31 (1 bit)


FDCAN_NDAT2

FDCAN new data 2 register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_NDAT2 FDCAN_NDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ND32 ND33 ND34 ND35 ND36 ND37 ND38 ND39 ND40 ND41 ND42 ND43 ND44 ND45 ND46 ND47 ND48 ND49 ND50 ND51 ND52 ND53 ND54 ND55 ND56 ND57 ND58 ND59 ND60 ND61 ND62 ND63

ND32 : ND32
bits : 0 - 0 (1 bit)

ND33 : ND33
bits : 1 - 1 (1 bit)

ND34 : ND34
bits : 2 - 2 (1 bit)

ND35 : ND35
bits : 3 - 3 (1 bit)

ND36 : ND36
bits : 4 - 4 (1 bit)

ND37 : ND37
bits : 5 - 5 (1 bit)

ND38 : ND38
bits : 6 - 6 (1 bit)

ND39 : ND39
bits : 7 - 7 (1 bit)

ND40 : ND40
bits : 8 - 8 (1 bit)

ND41 : ND41
bits : 9 - 9 (1 bit)

ND42 : ND42
bits : 10 - 10 (1 bit)

ND43 : ND43
bits : 11 - 11 (1 bit)

ND44 : ND44
bits : 12 - 12 (1 bit)

ND45 : ND45
bits : 13 - 13 (1 bit)

ND46 : ND46
bits : 14 - 14 (1 bit)

ND47 : ND47
bits : 15 - 15 (1 bit)

ND48 : ND48
bits : 16 - 16 (1 bit)

ND49 : ND49
bits : 17 - 17 (1 bit)

ND50 : ND50
bits : 18 - 18 (1 bit)

ND51 : ND51
bits : 19 - 19 (1 bit)

ND52 : ND52
bits : 20 - 20 (1 bit)

ND53 : ND53
bits : 21 - 21 (1 bit)

ND54 : ND54
bits : 22 - 22 (1 bit)

ND55 : ND55
bits : 23 - 23 (1 bit)

ND56 : ND56
bits : 24 - 24 (1 bit)

ND57 : ND57
bits : 25 - 25 (1 bit)

ND58 : ND58
bits : 26 - 26 (1 bit)

ND59 : ND59
bits : 27 - 27 (1 bit)

ND60 : ND60
bits : 28 - 28 (1 bit)

ND61 : ND61
bits : 29 - 29 (1 bit)

ND62 : ND62
bits : 30 - 30 (1 bit)

ND63 : ND63
bits : 31 - 31 (1 bit)


FDCAN_RXF0C

FDCAN Rx FIFO Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF0C FDCAN_RXF0C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0SA F0S F0WM F0OM

F0SA : F0SA
bits : 2 - 15 (14 bit)
access : read-write

F0S : F0S
bits : 16 - 22 (7 bit)
access : read-write

F0WM : F0WM
bits : 24 - 30 (7 bit)
access : read-write

F0OM : F0OM
bits : 31 - 31 (1 bit)
access : read-write


FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF0S FDCAN_RXF0S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0FL F0GI F0PI F0F RF0L

F0FL : F0FL
bits : 0 - 6 (7 bit)
access : read-write

F0GI : F0GI
bits : 8 - 13 (6 bit)
access : read-write

F0PI : F0PI
bits : 16 - 21 (6 bit)
access : read-write

F0F : F0F
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Rx FIFO 0 not full

0x1 : B_0x1

Rx FIFO 0 full

End of enumeration elements list.

RF0L : RF0L
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No Rx FIFO 0 message lost

0x1 : B_0x1

Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

End of enumeration elements list.


FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF0A FDCAN_RXF0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0AI

F0AI : F0AI
bits : 0 - 5 (6 bit)
access : read-write


FDCAN_RXBC

FDCAN Rx buffer configuration register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXBC FDCAN_RXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBSA

RBSA : RBSA
bits : 2 - 15 (14 bit)
access : read-write


FDCAN_RXF1C

FDCAN Rx FIFO 1 configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF1C FDCAN_RXF1C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1SA F1S F1WM F1OM

F1SA : F1SA
bits : 2 - 15 (14 bit)
access : read-write

F1S : F1S
bits : 16 - 22 (7 bit)
access : read-write

F1WM : F1WM
bits : 24 - 30 (7 bit)
access : read-write

F1OM : F1OM
bits : 31 - 31 (1 bit)
access : read-write


FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF1S FDCAN_RXF1S read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1FL F1GI F1PI F1F RF1L DMS

F1FL : F1FL
bits : 0 - 6 (7 bit)
access : read-only

F1GI : F1GI
bits : 8 - 13 (6 bit)
access : read-only

F1PI : F1PI
bits : 16 - 21 (6 bit)
access : read-only

F1F : F1F
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

Rx FIFO 1 not full

0x1 : B_0x1

Rx FIFO 1 full

End of enumeration elements list.

RF1L : RF1L
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No Rx FIFO 1 message lost

0x1 : B_0x1

Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.

End of enumeration elements list.

DMS : DMS
bits : 30 - 31 (2 bit)
access : read-only


FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF1A FDCAN_RXF1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1AI

F1AI : F1AI
bits : 0 - 5 (6 bit)
access : read-write


FDCAN_RXESC

Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXESC FDCAN_RXESC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0DS F1DS RBDS

F0DS : F0DS
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0x0 : B_0x0

8 byte data field

0x1 : B_0x1

12 byte data field

0x2 : B_0x2

16 byte data field

0x3 : B_0x3

20 byte data field

0x4 : B_0x4

24 byte data field

0x5 : B_0x5

32 byte data field

0x6 : B_0x6

48 byte data field

0x7 : B_0x7

64 byte data field

End of enumeration elements list.

F1DS : F1DS
bits : 4 - 6 (3 bit)
access : read-only

Enumeration:

0x0 : B_0x0

8 byte data field

0x1 : B_0x1

12 byte data field

0x2 : B_0x2

16 byte data field

0x3 : B_0x3

20 byte data field

0x4 : B_0x4

24 byte data field

0x5 : B_0x5

32 byte data field

0x6 : B_0x6

48 byte data field

0x7 : B_0x7

64 byte data field

End of enumeration elements list.

RBDS : RBDS
bits : 8 - 10 (3 bit)
access : read-only


FDCAN_DBTP

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_DBTP FDCAN_DBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSJW DTSEG2 DTSEG1 DBRP TDC

DSJW : DSJW
bits : 0 - 3 (4 bit)
access : read-write

DTSEG2 : DTSEG2
bits : 4 - 7 (4 bit)
access : read-write

DTSEG1 : DTSEG1
bits : 8 - 12 (5 bit)
access : write-only

DBRP : DBRP
bits : 16 - 20 (5 bit)
access : read-write

TDC : TDC
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

Transceiver Delay Compensation disabled

0x1 : B_0x1

Transceiver Delay Compensation enabled

End of enumeration elements list.


FDCAN_TXBC

FDCAN Tx Buffer Configuration Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBC FDCAN_TXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBSA NDTB TFQS TFQM

TBSA : TBSA
bits : 2 - 15 (14 bit)

NDTB : NDTB
bits : 16 - 21 (6 bit)

TFQS : TFQS
bits : 24 - 29 (6 bit)

TFQM : TFQM
bits : 30 - 30 (1 bit)


FDCAN_TXFQS

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXFQS FDCAN_TXFQS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFL TFGI TFQPI TFQF

TFFL : TFFL
bits : 0 - 5 (6 bit)
access : read-only

TFGI : TFGI
bits : 8 - 12 (5 bit)
access : read-only

TFQPI : TFQPI
bits : 16 - 20 (5 bit)
access : read-only

TFQF : TFQF
bits : 21 - 21 (1 bit)
access : read-only


FDCAN_TXESC

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes greater than 8 bytes are intended for CAN FD operation only.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXESC FDCAN_TXESC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBDS

TBDS : TBDS
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0x0 : B_0x0

8 byte data field

0x1 : B_0x1

12 byte data field

0x2 : B_0x2

16 byte data field

0x3 : B_0x3

20 byte data field

0x4 : B_0x4

24 byte data field

0x5 : B_0x5

32 byte data field

0x6 : B_0x6

48 byte data field

0x7 : B_0x7

64 byte data field

End of enumeration elements list.


FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBRP FDCAN_TXBRP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRP

TRP : TRP
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No transmission request pending

0x1 : B_0x1

Transmission request pending

End of enumeration elements list.


FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBAR FDCAN_TXBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR

AR : AR
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No transmission request added

0x1 : B_0x1

Transmission requested added.

End of enumeration elements list.


FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBCR FDCAN_TXBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR

CR : CR
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0x0 : B_0x0

No cancellation pending

0x1 : B_0x1

Cancellation pending

End of enumeration elements list.


FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBTO FDCAN_TXBTO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : TO
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No transmission occurred

0x1 : B_0x1

Transmission occurred

End of enumeration elements list.


FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBCF FDCAN_TXBCF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : CF
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No transmit buffer cancellation

0x1 : B_0x1

Transmit buffer cancellation finished

End of enumeration elements list.


FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBTIE FDCAN_TXBTIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE

TIE : TIE
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Transmission interrupt disabled

0x1 : B_0x1

Transmission interrupt enable

End of enumeration elements list.


FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBCIE FDCAN_TXBCIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFIE

CFIE : CFIE
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Cancellation finished interrupt disabled

0x1 : B_0x1

Cancellation finished interrupt enabled

End of enumeration elements list.


FDCAN_TXEFC

FDCAN Tx event FIFO configuration register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXEFC FDCAN_TXEFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFSA EFS EFWM

EFSA : EFSA
bits : 2 - 15 (14 bit)

EFS : EFS
bits : 16 - 21 (6 bit)

EFWM : EFWM
bits : 24 - 29 (6 bit)


FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXEFS FDCAN_TXEFS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFFL EFGI EFPI EFF TEFL

EFFL : EFFL
bits : 0 - 5 (6 bit)
access : read-only

EFGI : EFGI
bits : 8 - 12 (5 bit)
access : read-only

EFPI : EFPI
bits : 16 - 20 (5 bit)
access : read-only

EFF : EFF
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

Tx Event FIFO not full

0x1 : B_0x1

Tx Event FIFO full

End of enumeration elements list.

TEFL : TEFL
bits : 25 - 25 (1 bit)
access : read-only


FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXEFA FDCAN_TXEFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFAI

EFAI : EFAI
bits : 0 - 4 (5 bit)
access : read-write



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