Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
MDMA Global Interrupt/Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF0 : GIF0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF1 : GIF1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF2 : GIF2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF3 : GIF3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF4 : GIF4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF5 : GIF5
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF6 : GIF6
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF7 : GIF7
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF8 : GIF8
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF9 : GIF9
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF10 : GIF10
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF11 : GIF11
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF12 : GIF12
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF13 : GIF13
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF14 : GIF14
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF15 : GIF15
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF16 : GIF16
bits : 16 - 16 (1 bit)
GIF17 : GIF17
bits : 17 - 17 (1 bit)
GIF18 : GIF18
bits : 18 - 18 (1 bit)
GIF19 : GIF19
bits : 19 - 19 (1 bit)
GIF20 : GIF20
bits : 20 - 20 (1 bit)
GIF21 : GIF21
bits : 21 - 21 (1 bit)
GIF22 : GIF22
bits : 22 - 22 (1 bit)
GIF23 : GIF23
bits : 23 - 23 (1 bit)
GIF24 : GIF24
bits : 24 - 24 (1 bit)
GIF25 : GIF25
bits : 25 - 25 (1 bit)
GIF26 : GIF26
bits : 26 - 26 (1 bit)
GIF27 : GIF27
bits : 27 - 27 (1 bit)
GIF28 : GIF28
bits : 28 - 28 (1 bit)
GIF29 : GIF29
bits : 29 - 29 (1 bit)
GIF30 : GIF30
bits : 30 - 30 (1 bit)
GIF31 : GIF31
bits : 31 - 31 (1 bit)
MDMA channel 3 interrupt/status register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF3 : TEIF3
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF3 : CTCIF3
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF3 : BRTIF3
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF3 : BTIF3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF3 : TCIF3
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA3 : CRQA3
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 3 interrupt flag clear register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF3 : CTEIF3
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF3 : CCTCIF3
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF3 : CBRTIF3
bits : 2 - 2 (1 bit)
access : write-only
CBTIF3 : CBTIF3
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF3 : CLTCIF3
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 3 error status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 3 block number of data register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 3 source address register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 3 destination address register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 3 Block Repeat address Update register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 3 Link Address register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 3 Trigger and Bus selection Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 3 Mask address register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 3 Mask Data register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 4 interrupt/status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF4 : TEIF4
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF4 : CTCIF4
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF4 : BRTIF4
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF4 : BTIF4
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF4 : TCIF4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA4 : CRQA4
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 4 interrupt flag clear register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF4 : CTEIF4
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF4 : CCTCIF4
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF4 : CBRTIF4
bits : 2 - 2 (1 bit)
access : write-only
CBTIF4 : CBTIF4
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF4 : CLTCIF4
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 4 error status register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 4 block number of data register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 4 source address register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 4 destination address register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 4 Block Repeat address Update register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 4 Link Address register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 4 Trigger and Bus selection Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 4 Mask address register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 4 Mask Data register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 5 interrupt/status register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF5 : TEIF5
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF5 : CTCIF5
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF5 : BRTIF5
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF5 : BTIF5
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF5 : TCIF5
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA5 : CRQA5
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 5 interrupt flag clear register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF5 : CTEIF5
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF5 : CCTCIF5
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF5 : CBRTIF5
bits : 2 - 2 (1 bit)
access : write-only
CBTIF5 : CBTIF5
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF5 : CLTCIF5
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 5 error status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 5 block number of data register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 5 source address register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 5 destination address register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 5 Block Repeat address Update register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 5 Link Address register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 5 Trigger and Bus selection Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 5 Mask address register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 5 Mask Data register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 6 interrupt/status register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF6 : TEIF6
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF6 : CTCIF6
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF6 : BRTIF6
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF6 : BTIF6
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF6 : TCIF6
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA6 : CRQA6
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 6 interrupt flag clear register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF6 : CTEIF6
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF6 : CCTCIF6
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF6 : CBRTIF6
bits : 2 - 2 (1 bit)
access : write-only
CBTIF6 : CBTIF6
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF6 : CLTCIF6
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 6 error status register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 6 block number of data register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 6 source address register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 6 destination address register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 6 Block Repeat address Update register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 6 Link Address register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 6 Trigger and Bus selection Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 6 Mask address register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 6 Mask Data register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 7 interrupt/status register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF7 : TEIF7
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF7 : CTCIF7
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF7 : BRTIF7
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF7 : BTIF7
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF7 : TCIF7
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA7 : CRQA7
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 7 interrupt flag clear register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF7 : CTEIF7
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF7 : CCTCIF7
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF7 : CBRTIF7
bits : 2 - 2 (1 bit)
access : write-only
CBTIF7 : CBTIF7
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF7 : CLTCIF7
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 7 error status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 7 block number of data register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 7 source address register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 7 destination address register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 7 Block Repeat address Update register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 7 Link Address register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 7 Trigger and Bus selection Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 7 Mask address register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 7 Mask Data register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 8 interrupt/status register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF8 : TEIF8
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF8 : CTCIF8
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF8 : BRTIF8
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF8 : BTIF8
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF8 : TCIF8
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA8 : CRQA8
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 8 interrupt flag clear register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF8 : CTEIF8
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF8 : CCTCIF8
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF8 : CBRTIF8
bits : 2 - 2 (1 bit)
access : write-only
CBTIF8 : CBTIF8
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF8 : CLTCIF8
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 8 error status register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 8 block number of data register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 8 source address register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 8 destination address register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 8 Block Repeat address Update register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 8 Link Address register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 8 Trigger and Bus selection Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 8 Mask address register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 8 Mask Data register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 9 interrupt/status register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF9 : TEIF9
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF9 : CTCIF9
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF9 : BRTIF9
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF9 : BTIF9
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF9 : TCIF9
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA9 : CRQA9
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 9 interrupt flag clear register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF9 : CTEIF9
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF9 : CCTCIF9
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF9 : CBRTIF9
bits : 2 - 2 (1 bit)
access : write-only
CBTIF9 : CBTIF9
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF9 : CLTCIF9
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 9 error status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 9 block number of data register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 9 source address register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 9 destination address register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 9 Block Repeat address Update register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 9 Link Address register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 9 Trigger and Bus selection Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 9 Mask address register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 9 Mask Data register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 10 interrupt/status register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF10 : TEIF10
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF10 : CTCIF10
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF10 : BRTIF10
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF10 : BTIF10
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF10 : TCIF10
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA10 : CRQA10
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 10 interrupt flag clear register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF10 : CTEIF10
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF10 : CCTCIF10
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF10 : CBRTIF10
bits : 2 - 2 (1 bit)
access : write-only
CBTIF10 : CBTIF10
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF10 : CLTCIF10
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 10 error status register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 10 block number of data register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 10 source address register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 10 destination address register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 10 Block Repeat address Update register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 10 Link Address register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 10 Trigger and Bus selection Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 10 Mask address register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 10 Mask Data register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 11 interrupt/status register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF11 : TEIF11
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF11 : CTCIF11
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF11 : BRTIF11
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF11 : BTIF11
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF11 : TCIF11
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA11 : CRQA11
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 11 interrupt flag clear register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF11 : CTEIF11
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF11 : CCTCIF11
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF11 : CBRTIF11
bits : 2 - 2 (1 bit)
access : write-only
CBTIF11 : CBTIF11
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF11 : CLTCIF11
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 11 error status register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 11 block number of data register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 11 source address register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 11 destination address register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 11 Block Repeat address Update register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 11 Link Address register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 11 Trigger and Bus selection Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 11 Mask address register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 11 Mask Data register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 12 interrupt/status register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF12 : TEIF12
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF12 : CTCIF12
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF12 : BRTIF12
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF12 : BTIF12
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF12 : TCIF12
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA12 : CRQA12
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 12 interrupt flag clear register
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF12 : CTEIF12
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF12 : CCTCIF12
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF12 : CBRTIF12
bits : 2 - 2 (1 bit)
access : write-only
CBTIF12 : CBTIF12
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF12 : CLTCIF12
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 12 error status register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 12 block number of data register
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 12 source address register
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 12 destination address register
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 12 Block Repeat address Update register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 12 Link Address register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 12 Trigger and Bus selection Register
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 12 Mask address register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 12 Mask Data register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 13 interrupt/status register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF13 : TEIF13
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF13 : CTCIF13
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF13 : BRTIF13
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF13 : BTIF13
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF13 : TCIF13
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA13 : CRQA13
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 13 interrupt flag clear register
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF13 : CTEIF13
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF13 : CCTCIF13
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF13 : CBRTIF13
bits : 2 - 2 (1 bit)
access : write-only
CBTIF13 : CBTIF13
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF13 : CLTCIF13
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 13 error status register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 13 block number of data register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 13 source address register
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 13 destination address register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 13 Block Repeat address Update register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 13 Link Address register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 13 Trigger and Bus selection Register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 13 Mask address register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 13 Mask Data register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 14 interrupt/status register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF14 : TEIF14
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF14 : CTCIF14
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF14 : BRTIF14
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF14 : BTIF14
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF14 : TCIF14
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA14 : CRQA14
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 14 interrupt flag clear register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF14 : CTEIF14
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF14 : CCTCIF14
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF14 : CBRTIF14
bits : 2 - 2 (1 bit)
access : write-only
CBTIF14 : CBTIF14
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF14 : CLTCIF14
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 14 error status register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 14 block number of data register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 14 source address register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 14 destination address register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 14 Block Repeat address Update register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 14 Link Address register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 14 Trigger and Bus selection Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 14 Mask address register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 14 Mask Data register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 interrupt/status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF0 : TEIF0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF0 : CTCIF0
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF0 : BRTIF0
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF0 : BTIF0
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF0 : TCIF0
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA0 : CRQA0
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 15 interrupt/status register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 15 interrupt flag clear register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 15 error status register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 15 block number of data register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 15 source address register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 15 destination address register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 15 Block Repeat address Update register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 15 Link Address register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 15 Trigger and Bus selection Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 15 Mask address register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 15 Mask Data register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 interrupt flag clear register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF0 : CTEIF0
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF0 : CCTCIF0
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF0 : CBRTIF0
bits : 2 - 2 (1 bit)
access : write-only
CBTIF0 : CBTIF0
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF0 : CLTCIF0
bits : 4 - 4 (1 bit)
access : write-only
MDMA channel 16 interrupt/status register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 16 interrupt flag clear register
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 16 error status register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA Channel 0 error status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
MDMA channel 17 interrupt/status register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 17 interrupt flag clear register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 17 error status register
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
This register is used to control the concerned channel.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
MDMA channel 18 interrupt/status register
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 18 interrupt flag clear register
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 18 error status register
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
This register is used to configure the concerned channel.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA channel 19 interrupt/status register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 19 interrupt flag clear register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 19 error status register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA Channel 0 block number of data register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 20 interrupt/status register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 20 interrupt flag clear register
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 20 error status register
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 source address register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 21 interrupt/status register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 21 interrupt flag clear register
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 21 error status register
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 destination address register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 22 interrupt/status register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 22 interrupt flag clear register
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 22 error status register
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 Block Repeat address Update register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 23 interrupt/status register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 23 interrupt flag clear register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 23 error status register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 Link Address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 24 interrupt/status register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 24 interrupt flag clear register
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 24 error status register
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 Trigger and Bus selection Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 25 interrupt/status register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 25 interrupt flag clear register
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 25 error status register
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 26 interrupt/status register
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 26 interrupt flag clear register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 26 error status register
address_offset : 0x6C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x6D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 Mask address register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 27 interrupt/status register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 27 interrupt flag clear register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 27 error status register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 0 Mask Data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 28 interrupt/status register
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 28 interrupt flag clear register
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 28 error status register
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 29 interrupt/status register
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 29 interrupt flag clear register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 29 error status register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 30 interrupt/status register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 30 interrupt flag clear register
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 30 error status register
address_offset : 0x7C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x7D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x7D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x7DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x7E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA secure global interrupt/status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF0 : GIF0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF1 : GIF1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF2 : GIF2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF3 : GIF3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF4 : GIF4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF5 : GIF5
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF6 : GIF6
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF7 : GIF7
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF8 : GIF8
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF9 : GIF9
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF10 : GIF10
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF11 : GIF11
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF12 : GIF12
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF13 : GIF13
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF14 : GIF14
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF15 : GIF15
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt generated by channel
x
0x1 : B_0x1
Interrupt generated by channel
x
End of enumeration elements list.
GIF16 : GIF16
bits : 16 - 16 (1 bit)
GIF17 : GIF17
bits : 17 - 17 (1 bit)
GIF18 : GIF18
bits : 18 - 18 (1 bit)
GIF19 : GIF19
bits : 19 - 19 (1 bit)
GIF20 : GIF20
bits : 20 - 20 (1 bit)
GIF21 : GIF21
bits : 21 - 21 (1 bit)
GIF22 : GIF22
bits : 22 - 22 (1 bit)
GIF23 : GIF23
bits : 23 - 23 (1 bit)
GIF24 : GIF24
bits : 24 - 24 (1 bit)
GIF25 : GIF25
bits : 25 - 25 (1 bit)
GIF26 : GIF26
bits : 26 - 26 (1 bit)
GIF27 : GIF27
bits : 27 - 27 (1 bit)
GIF28 : GIF28
bits : 28 - 28 (1 bit)
GIF29 : GIF29
bits : 29 - 29 (1 bit)
GIF30 : GIF30
bits : 30 - 30 (1 bit)
GIF31 : GIF31
bits : 31 - 31 (1 bit)
MDMA channel 1 interrupt/status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF1 : TEIF1
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF1 : CTCIF1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF1 : BRTIF1
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF1 : BTIF1
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF1 : TCIF1
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA1 : CRQA1
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 31 interrupt/status register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF15 : TEIF15
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF15 : CTCIF15
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF15 : BRTIF15
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF15 : BTIF15
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF15 : TCIF15
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA15 : CRQA15
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 31 interrupt flag clear register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF15 : CTEIF15
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF15 : CCTCIF15
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF15 : CBRTIF15
bits : 2 - 2 (1 bit)
access : write-only
CBTIF15 : CBTIF15
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF15 : CLTCIF15
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 31 error status register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel block number of data register
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel source address register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel destination address register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Block Repeat address Update register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel Link Address register
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Trigger and Bus selection Register
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel Mask address register
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel Mask Data register
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 1 interrupt flag clear register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF1 : CTEIF1
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF1 : CCTCIF1
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF1 : CBRTIF1
bits : 2 - 2 (1 bit)
access : write-only
CBTIF1 : CBTIF1
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF1 : CLTCIF1
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 1 error status register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 1 block number of data register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 1 source address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 1 destination address register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 1 Block Repeat address Update register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 1 Link Address register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 1 Trigger and Bus selection Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 1 Mask address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 1 Mask Data register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 2 interrupt/status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF2 : TEIF2
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No transfer error on stream
x
0x1 : B_0x1
A transfer error occurred on stream
x
End of enumeration elements list.
CTCIF2 : CTCIF2
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No channel transfer complete event
on channel x
0x1 : B_0x1
A channel transfer complete event
occurred on channel x
End of enumeration elements list.
BRTIF2 : BRTIF2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block repeat transfer complete
event on channel x
0x1 : B_0x1
A block repeat transfer complete
event occurred on channel x
End of enumeration elements list.
BTIF2 : BTIF2
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block transfer complete event on
channel x
0x1 : B_0x1
A block transfer complete event
occurred on channel x
End of enumeration elements list.
TCIF2 : TCIF2
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No buffer transfer complete event on
channel x
0x1 : B_0x1
A buffer transfer complete event
occurred on channel x
End of enumeration elements list.
CRQA2 : CRQA2
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MDMA transfer RQ is inactive for
channel x.
0x1 : B_0x1
The MDMA transfer RQ is active for
channel x
End of enumeration elements list.
MDMA channel 2 interrupt flag clear register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF2 : CTEIF2
bits : 0 - 0 (1 bit)
access : write-only
CCTCIF2 : CCTCIF2
bits : 1 - 1 (1 bit)
access : write-only
CBRTIF2 : CBRTIF2
bits : 2 - 2 (1 bit)
access : write-only
CBTIF2 : CBTIF2
bits : 3 - 3 (1 bit)
access : write-only
CLTCIF2 : CLTCIF2
bits : 4 - 4 (1 bit)
access : write-only
MDMA Channel 2 error status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
access : read-only
TED : TED
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The last transfer error on the
channel was a related to a read
access.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write
access.
End of enumeration elements list.
TELD : TELD
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No link data read access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a read of the Link Data
structure.
End of enumeration elements list.
TEMD : TEMD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No mask write access
error.
0x1 : B_0x1
The last transfer error on the
channel was a related to a write of the Mask
Data.
End of enumeration elements list.
ASE : ASE
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No address/size error.
0x1 : B_0x1
Programmed address is not coherent
with the data size.
End of enumeration elements list.
BSE : BSE
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No block size error.
0x1 : B_0x1
Programmed block size is not an
integer multiple of the data size.
End of enumeration elements list.
This register is used to control the concerned channel.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel disabled
0x1 : B_0x1
Channel enabled
End of enumeration elements list.
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TE interrupt disabled
0x1 : B_0x1
TE interrupt enabled
End of enumeration elements list.
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT interrupt disabled
0x1 : B_0x1
BT interrupt enabled
End of enumeration elements list.
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BT complete interrupt
disabled
0x1 : B_0x1
BT complete interrupt
enabled
End of enumeration elements list.
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TC interrupt disabled
0x1 : B_0x1
TC interrupt enabled
End of enumeration elements list.
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low
0x1 : B_0x1
Medium
0x2 : B_0x2
High
0x3 : B_0x3
Very high
End of enumeration elements list.
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
bytes
0x1 : B_0x1
byte order exchanged in each
half-word
End of enumeration elements list.
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for half
words
0x1 : B_0x1
half-word order exchanged in each
word
End of enumeration elements list.
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Little endianess preserved for
words
0x1 : B_0x1
word order exchanged in double
word
End of enumeration elements list.
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source address pointer is
fixed
0x2 : B_0x2
Source address pointer is
incremented after each data transfer (increment
is done according to SINCOS)
0x3 : B_0x3
Source address pointer is
decremented after each data transfer (increment
is done according to SINCOS)
End of enumeration elements list.
DINC : DINC
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Destination address pointer is
fixed
0x2 : B_0x2
Destination address pointer is
incremented after each data transfer (increment
is done according to DINCOS)
0x3 : B_0x3
Destination address pointer is
decremented after each data transfer (increment
is done according to DINCOS)
End of enumeration elements list.
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Byte (8-bit)
0x1 : B_0x1
Half-word (16-bit)
0x2 : B_0x2
Word (32-bit)
0x3 : B_0x3
Double-Word (64-bit)
End of enumeration elements list.
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
byte (8-bit)
0x1 : B_0x1
half-word (16-bit)
0x2 : B_0x2
word (32-bit)
0x3 : B_0x3
Double-Word (64-bit) -
End of enumeration elements list.
SBURST : SBURST
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats
End of enumeration elements list.
DBURST : DBURST
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
single transfer N: burst of 2^N
beats These bits are protected and can be written
only if EN is 0
End of enumeration elements list.
TLEN : TLEN
bits : 18 - 24 (7 bit)
access : read-write
PKE : PKE
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The source data is written to the
destination as is.
0x1 : B_0x1
The source data is packed/un-packed
into the destination data size. All data are
right aligned, in Little Endian
mode.
End of enumeration elements list.
PAM : PAM
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right Aligned - only the LSBs part
of the Source is written to the destination
address
0x1 : B_0x1
Right Aligned, Sign
extended
0x2 : B_0x2
Left Aligned - only the MSBs part of
the Source is written to the destination
address
End of enumeration elements list.
TRGM : TRGM
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each MDMA request (SW or HW)
triggers a buffer transfer
0x1 : B_0x1
Each MDMA request (SW or HW)
triggers a block transfer
0x2 : B_0x2
Each MDMA request (SW or HW)
triggers a repeated block transfer (if the block
repeat is 0, a single block is
transferred)
0x3 : B_0x3
Each MDMA request (SW or HW)
triggers the transfer of the whole data for the
respective channel (e.g. linked list) until the
channel reach the end and it is
disabled.
End of enumeration elements list.
SWRM : SWRM
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HW request are taken into account:
the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx
signal.
0x1 : B_0x1
HW request are ignored. Transfer is
trigerred by SW writing 1 to the SWRQ
bit.
End of enumeration elements list.
BWM : BWM
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The destination write operation is
non-bufferable.
0x1 : B_0x1
The destination write operation is
bufferable.
End of enumeration elements list.
MDMA Channel 2 block number of data register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
access : read-write
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a block transfer, the
SAR register will be updated by adding the SUV to
the current SAR value (current Source
Address)
0x1 : B_0x1
At the end of a block transfer, the
SAR register will be updated by subtracting the
SUV from the current SAR value (current Source
Address)
End of enumeration elements list.
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
At the end of a Block transfer, the
DAR register will be updated by adding the DUV to
the current DAR value (current Destination
Address)
0x1 : B_0x1
At the end of a block transfer, the
DAR register will be updated by subtracting the
DUV from the current DAR value (current
Destination Address)
End of enumeration elements list.
BRC : BRC
bits : 20 - 31 (12 bit)
access : read-write
MDMA channel 2 source address register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 2 destination address register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 2 Block Repeat address Update register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
access : read-write
DUV : DUV
bits : 16 - 31 (16 bit)
access : read-write
MDMA channel 2 Link Address register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 2 Trigger and Bus selection Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
access : read-write
SBUS : SBUS
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as source
(read operation) on channel x.
0x1 : B_0x1
The AHB bus/TCM is used as source
(read operation) on channel x.
End of enumeration elements list.
DBUS : DBUS
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The system/AXI bus is used as
destination (write operation) on channel
x.
0x1 : B_0x1
The AHB bus/TCM is used as
destination (write operation) on channel
x.
End of enumeration elements list.
MDMA channel 2 Mask address register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
access : read-write
MDMA channel 2 Mask Data register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
access : read-write
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