Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
RCC_TZAHB6RSTSETR (TZAHB6RSTSETR)
RCC_TZAHB6RSTCLRR (TZAHB6RSTCLRR)
RCC_MP_APB4ENSETR (MP_APB4ENSETR)
RCC_MP_APB4ENCLRR (MP_APB4ENCLRR)
RCC_MP_APB5ENSETR (MP_APB5ENSETR)
RCC_MP_APB5ENCLRR (MP_APB5ENCLRR)
RCC_MP_AHB5ENSETR (MP_AHB5ENSETR)
RCC_MP_AHB5ENCLRR (MP_AHB5ENCLRR)
RCC_MP_AHB6ENSETR (MP_AHB6ENSETR)
RCC_MP_AHB6ENCLRR (MP_AHB6ENCLRR)
RCC_MP_TZAHB6ENSETR (MP_TZAHB6ENSETR)
RCC_MP_TZAHB6ENCLRR (MP_TZAHB6ENCLRR)
RCC_MC_APB4ENSETR (MC_APB4ENSETR)
RCC_MC_APB4ENCLRR (MC_APB4ENCLRR)
RCC_MC_APB5ENSETR (MC_APB5ENSETR)
RCC_MC_APB5ENCLRR (MC_APB5ENCLRR)
RCC_MC_AHB5ENSETR (MC_AHB5ENSETR)
RCC_MC_AHB5ENCLRR (MC_AHB5ENCLRR)
RCC_MC_AHB6ENSETR (MC_AHB6ENSETR)
RCC_MC_AHB6ENCLRR (MC_AHB6ENCLRR)
RCC_MP_APB4LPENSETR (MP_APB4LPENSETR)
RCC_MP_APB4LPENCLRR (MP_APB4LPENCLRR)
RCC_MP_APB5LPENSETR (MP_APB5LPENSETR)
RCC_MP_APB5LPENCLRR (MP_APB5LPENCLRR)
RCC_MP_AHB5LPENSETR (MP_AHB5LPENSETR)
RCC_MP_AHB5LPENCLRR (MP_AHB5LPENCLRR)
RCC_MP_AHB6LPENSETR (MP_AHB6LPENSETR)
RCC_MP_AHB6LPENCLRR (MP_AHB6LPENCLRR)
RCC_MP_TZAHB6LPENSETR (MP_TZAHB6LPENSETR)
RCC_MP_TZAHB6LPENCLRR (MP_TZAHB6LPENCLRR)
RCC_MC_APB4LPENSETR (MC_APB4LPENSETR)
RCC_MC_APB4LPENCLRR (MC_APB4LPENCLRR)
RCC_MC_APB5LPENSETR (MC_APB5LPENSETR)
RCC_MC_APB5LPENCLRR (MC_APB5LPENCLRR)
RCC_MC_AHB5LPENSETR (MC_AHB5LPENSETR)
RCC_MC_AHB5LPENCLRR (MC_AHB5LPENCLRR)
RCC_MC_AHB6LPENSETR (MC_AHB6LPENSETR)
RCC_MC_AHB6LPENCLRR (MC_AHB6LPENCLRR)
RCC_MP_GRSTCSETR (MP_GRSTCSETR)
RCC_MP_IWDGFZSETR (MP_IWDGFZSETR)
RCC_MP_IWDGFZCLRR (MP_IWDGFZCLRR)
RCC_SPI2S1CKSELR (SPI2S1CKSELR)
RCC_SPI2S23CKSELR (SPI2S23CKSELR)
RCC_UART24CKSELR (UART24CKSELR)
RCC_UART35CKSELR (UART35CKSELR)
RCC_UART78CKSELR (UART78CKSELR)
RCC_SDMMC12CKSELR (SDMMC12CKSELR)
RCC_SDMMC3CKSELR (SDMMC3CKSELR)
RCC_LPTIM45CKSELR (LPTIM45CKSELR)
RCC_LPTIM23CKSELR (LPTIM23CKSELR)
RCC_LPTIM1CKSELR (LPTIM1CKSELR)
RCC_MP_APB1ENSETR (MP_APB1ENSETR)
RCC_MP_APB1ENCLRR (MP_APB1ENCLRR)
RCC_MP_APB2ENSETR (MP_APB2ENSETR)
RCC_MP_APB2ENCLRR (MP_APB2ENCLRR)
RCC_MP_APB3ENSETR (MP_APB3ENSETR)
RCC_MP_APB3ENCLRR (MP_APB3ENCLRR)
RCC_MP_AHB2ENSETR (MP_AHB2ENSETR)
RCC_MP_AHB2ENCLRR (MP_AHB2ENCLRR)
RCC_MP_AHB3ENSETR (MP_AHB3ENSETR)
RCC_MP_AHB3ENCLRR (MP_AHB3ENCLRR)
RCC_MP_AHB4ENSETR (MP_AHB4ENSETR)
RCC_MP_AHB4ENCLRR (MP_AHB4ENCLRR)
RCC_MP_MLAHBENSETR (MP_MLAHBENSETR)
RCC_MP_MLAHBENCLRR (MP_MLAHBENCLRR)
RCC_MC_APB1ENSETR (MC_APB1ENSETR)
RCC_MC_APB1ENCLRR (MC_APB1ENCLRR)
RCC_MC_APB2ENSETR (MC_APB2ENSETR)
RCC_MC_APB2ENCLRR (MC_APB2ENCLRR)
RCC_MC_APB3ENSETR (MC_APB3ENSETR)
RCC_MC_APB3ENCLRR (MC_APB3ENCLRR)
RCC_MC_AHB2ENSETR (MC_AHB2ENSETR)
RCC_MC_AHB2ENCLRR (MC_AHB2ENCLRR)
RCC_MC_AHB3ENSETR (MC_AHB3ENSETR)
RCC_MC_AHB3ENCLRR (MC_AHB3ENCLRR)
RCC_MC_AHB4ENSETR (MC_AHB4ENSETR)
RCC_MC_AHB4ENCLRR (MC_AHB4ENCLRR)
RCC_MC_AXIMENSETR (MC_AXIMENSETR)
RCC_MC_AXIMENCLRR (MC_AXIMENCLRR)
RCC_MC_MLAHBENSETR (MC_MLAHBENSETR)
RCC_MC_MLAHBENCLRR (MC_MLAHBENCLRR)
RCC_MP_APB1LPENSETR (MP_APB1LPENSETR)
RCC_MP_APB1LPENCLRR (MP_APB1LPENCLRR)
RCC_MP_APB2LPENSETR (MP_APB2LPENSETR)
RCC_MP_APB2LPENCLRR (MP_APB2LPENCLRR)
RCC_MP_APB3LPENSETR (MP_APB3LPENSETR)
RCC_MP_APB3LPENCLRR (MP_APB3LPENCLRR)
RCC_MP_AHB2LPENSETR (MP_AHB2LPENSETR)
RCC_MP_AHB2LPENCLRR (MP_AHB2LPENCLRR)
RCC_MP_AHB3LPENSETR (MP_AHB3LPENSETR)
RCC_MP_AHB3LPENCLRR (MP_AHB3LPENCLRR)
RCC_MP_AHB4LPENSETR (MP_AHB4LPENSETR)
RCC_MP_AHB4LPENCLRR (MP_AHB4LPENCLRR)
RCC_MP_AXIMLPENSETR (MP_AXIMLPENSETR)
RCC_MP_AXIMLPENCLRR (MP_AXIMLPENCLRR)
RCC_MP_MLAHBLPENSETR (MP_MLAHBLPENSETR)
RCC_MP_MLAHBLPENCLRR (MP_MLAHBLPENCLRR)
RCC_MC_APB1LPENSETR (MC_APB1LPENSETR)
RCC_MC_APB1LPENCLRR (MC_APB1LPENCLRR)
RCC_MC_APB2LPENSETR (MC_APB2LPENSETR)
RCC_MC_APB2LPENCLRR (MC_APB2LPENCLRR)
RCC_MC_APB3LPENSETR (MC_APB3LPENSETR)
RCC_MC_APB3LPENCLRR (MC_APB3LPENCLRR)
RCC_MC_AHB2LPENSETR (MC_AHB2LPENSETR)
RCC_MC_AHB2LPENCLRR (MC_AHB2LPENCLRR)
RCC_MC_AHB3LPENSETR (MC_AHB3LPENSETR)
RCC_MC_AHB3LPENCLRR (MC_AHB3LPENCLRR)
RCC_MC_AHB4LPENSETR (MC_AHB4LPENSETR)
RCC_MC_AHB4LPENCLRR (MC_AHB4LPENCLRR)
RCC_MC_AXIMLPENSETR (MC_AXIMLPENSETR)
RCC_MC_AXIMLPENCLRR (MC_AXIMLPENCLRR)
RCC_MC_MLAHBLPENSETR (MC_MLAHBLPENSETR)
RCC_MC_MLAHBLPENCLRR (MC_MLAHBLPENCLRR)
This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZEN : TZEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No protection
0x1 : B_0x1
TrustZone enabled (default after
reset).
End of enumeration elements list.
MCKPROT : MCKPROT
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The registers controlling mcuss_ck
clock are not protected
0x1 : B_0x1
The registers controlling mcuss_ck
clock are protected, (default after
reset).
End of enumeration elements list.
This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSION : HSION
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the HSION bit
End of enumeration elements list.
HSIKERON : HSIKERON
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the HSIKERON bit
End of enumeration elements list.
CSION : CSION
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CSI is OFF
0x1 : B_0x1
Clear the CSION bit
End of enumeration elements list.
CSIKERON : CSIKERON
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the CSIKERON bit
End of enumeration elements list.
DIGBYP : DIGBYP
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the DIGBYP bit (analog
bypass)
End of enumeration elements list.
HSEON : HSEON
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the HSEON bit
End of enumeration elements list.
HSEKERON : HSEKERON
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the HSEKERON bit
End of enumeration elements list.
HSEBYP : HSEBYP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the HSEBYP bit
End of enumeration elements list.
This register is used to control the HOLD boot function when the system exits from STANDBY. Please refer to Section1.3.13.5: MCU HOLD_BOOT After Processor Reset. This register is reset when a system reset occurs, but not when the circuit exits from STANDBY (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_BEN : MCU_BEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The MCU will remain on HOLD_BOOT
when the system exits from STANDBY
0x1 : B_0x1
The MCU is allowed to restart when
the system exits from STANDBY
End of enumeration elements list.
MPU_BEN : MPU_BEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The MPU will remain on CSTANDBY when
the system exits from STANDBY
0x1 : B_0x1
The MPU is allowed to restart when
the system exits from STANDBY
End of enumeration elements list.
Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPREQ_P0 : STPREQ_P0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the MPU processor number 0 does not allow
the MPU domain to go to CSTOP
0x1 : B_0x1
Writing clears the STPREQ_P0 bit,
reading means that the MPU processor number 0
allows the MPU domain to go to
CSTOP
End of enumeration elements list.
STPREQ_P1 : STPREQ_P1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the MPU processor number 1 does not allow
the MPU domain to go to CSTOP
0x1 : B_0x1
Writing sets the STPREQ_P1 bit,
reading means that the MPU processor number 1
allows the MPU domain to go to
CSTOP
End of enumeration elements list.
Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPREQ_P0 : STPREQ_P0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the MPU processor number 0 does not allow
the MPU domain to go to CSTOP
0x1 : B_0x1
Writing clears the STPREQ_P0 bit,
reading means that the MPU processor number 0
allows the MPU domain to go to
CSTOP
End of enumeration elements list.
STPREQ_P1 : STPREQ_P1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the MPU processor number 1 does not allow
the MPU domain to go to CSTOP
0x1 : B_0x1
Writing clears the STPREQ_P1 bit,
reading means that the MPU processor number 1
allows the MPU domain to go to
CSTOP
End of enumeration elements list.
The register contains global control bits. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOT_MCU : BOOT_MCU
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The MCU will be set in HOLD_BOOT
when the next MCU core reset occurs. (default
after reset)
0x1 : B_0x1
The MCU will not be in HOLD_BOOT
mode when the next MCU core reset
occurs.
End of enumeration elements list.
This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDCTLEN : RDCTLEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The RDCTL control block is bypassed
(default after reset)
0x1 : B_0x1
The RDCTL control block is
enabled.
End of enumeration elements list.
RSTTO : RSTTO
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The timeout function is disabled
(default after reset)
0x1 : B_0x1
The timeout is set to 2 x 2HSIDIV
us
0x7F : B_0x7F
The timeout is set to 128 x 2HSIDIV
us
End of enumeration elements list.
This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSTTOV : RSTTOV
bits : 8 - 14 (7 bit)
access : read-only
This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section1.3.5: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSEON : LSEON
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE oscillator OFF (default after
backup domain reset)
0x1 : B_0x1
LSE oscillator ON
End of enumeration elements list.
LSEBYP : LSEBYP
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE oscillator not bypassed (default
after backup domain reset)
0x1 : B_0x1
LSE oscillator
bypassed
End of enumeration elements list.
LSERDY : LSERDY
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LSE oscillator not ready (default
after backup domain reset)
0x1 : B_0x1
LSE oscillator ready
End of enumeration elements list.
LSEDRV : LSEDRV
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Lowest drive (default after backup
domain reset)
0x1 : B_0x1
Medium low drive
0x2 : B_0x2
Medium high drive
0x3 : B_0x3
Highest drive
End of enumeration elements list.
LSECSSON : LSECSSON
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock Security System on 32 kHz
oscillator OFF (default after backup domain
reset)
0x1 : B_0x1
Clock Security System on 32 kHz
oscillator ON
End of enumeration elements list.
LSECSSD : LSECSSD
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No failure detected on 32 kHz
oscillator (default after backup domain
reset)
0x1 : B_0x1
Failure detected on 32 kHz
oscillator
End of enumeration elements list.
RTCSRC : RTCSRC
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock (default after backup
domain reset)
0x1 : B_0x1
LSE clock used as RTC
clock
0x2 : B_0x2
LSI clock used as RTC
clock
0x3 : B_0x3
HSE clock divided by RTCDIV value is
used as RTC clock
End of enumeration elements list.
RTCCKEN : RTCCKEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
rtc_ck clock is disabled (default
after backup domain reset)
0x1 : B_0x1
rtc_ck clock enabled
End of enumeration elements list.
VSWRST : VSWRST
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Reset not activated (default after
backup domain reset)
0x1 : B_0x1
Resets the entire VSW
domain
End of enumeration elements list.
This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSION : LSION
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI oscillator OFF (default after
reset)
0x1 : B_0x1
LSI oscillator ON
End of enumeration elements list.
LSIRDY : LSIRDY
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LSI oscillator not ready (default
after reset)
0x1 : B_0x1
LSI oscillator ready
End of enumeration elements list.
MRD : MRD
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
NRST low pulse duration is
guaranteed by the pulse stretcher of the PAD. The
RPCTL is bypassed (default after
reset)
0x1 : B_0x1
The guaranteed NRST low pulse
duration is about 1 ms (1 x 32 lsi_ck
cycles),
0x2 : B_0x2
The guaranteed NRST low pulse
duration is about 2 ms (2 x 32 lsi_ck
cycles),
0x1F : B_0x1F
The guaranteed NRST low pulse
duration is about 31 ms (31 x 32 lsi_ck
cycles).
End of enumeration elements list.
EADLY : EADLY
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
10 ms (default after
reset)
0x1 : B_0x1
No extra delay added by the
BOOTROM
0x2 : B_0x2
100 us
0x3 : B_0x3
200 us
0x4 : B_0x4
500 us
0x5 : B_0x5
1 ms
0x6 : B_0x6
2 ms
0x7 : B_0x7
5 ms
End of enumeration elements list.
SPARE : SPARE
bits : 27 - 31 (5 bit)
access : read-write
This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSIDIV : HSIDIV
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Division by 1, hsi_ck (hsi_ker_ck) =
64 MHz (default after reset)
0x1 : B_0x1
Division by 2, hsi_ck (hsi_ker_ck) =
32 MHz
0x2 : B_0x2
Division by 4, hsi_ck (hsi_ker_ck) =
16 MHz
0x3 : B_0x3
Division by 8, hsi_ck (hsi_ker_ck) =
8 MHz
End of enumeration elements list.
HSITRIM : HSITRIM
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bsec_hsi_cal[11:0] (default after
reset)
0x3E : B_0x3E
bsec_hsi_cal[11:0] +
62
0x3F : B_0x3F
bsec_hsi_cal[11:0] +
63
0x40 : B_0x40
bsec_hsi_cal[11:0] -
64
0x41 : B_0x41
bsec_hsi_cal[11:0] -
63
End of enumeration elements list.
HSICAL : HSICAL
bits : 16 - 27 (12 bit)
access : read-only
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCRST : LTDCRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DSIRST : DSIRST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DDRPERFMRST : DDRPERFMRST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USBPHYRST : USBPHYRST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCRST : LTDCRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DSIRST : DSIRST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DDRPERFMRST : DDRPERFMRST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USBPHYRST : USBPHYRST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6RST : SPI6RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C4RST : I2C4RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C6RST : I2C6RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART1RST : USART1RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
STGENRST : STGENRST
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6RST : SPI6RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C4RST : I2C4RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C6RST : I2C6RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART1RST : USART1RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
STGENRST : STGENRST
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZRST : GPIOZRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRYP1RST : CRYP1RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
HASH1RST : HASH1RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
RNG1RST : RNG1RST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
AXIMCRST : AXIMCRST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZRST : GPIOZRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRYP1RST : CRYP1RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
HASH1RST : HASH1RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
RNG1RST : RNG1RST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
AXIMCRST : AXIMCRST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPURST : GPURST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
on-going
End of enumeration elements list.
ETHMACRST : ETHMACRST
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
FMCRST : FMCRST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
QSPIRST : QSPIRST
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SDMMC1RST : SDMMC1RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SDMMC2RST : SDMMC2RST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRC1RST : CRC1RST
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USBHRST : USBHRST
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHMACRST : ETHMACRST
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
FMCRST : FMCRST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
QSPIRST : QSPIRST
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SDMMC1RST : SDMMC1RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SDMMC2RST : SDMMC2RST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRC1RST : CRC1RST
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USBHRST : USBHRST
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMARST : MDMARST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMARST : MDMARST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSITRIM : CSITRIM
bits : 8 - 12 (5 bit)
access : read-write
CSICAL : CSICAL
bits : 16 - 23 (8 bit)
access : read-only
This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPUSRC : MPUSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI selected as system clock
(hsi_ck) (default after reset)
0x1 : B_0x1
HSE selected as system clock
(hse_ck)
0x2 : B_0x2
PLL1 selected as system clock
(pll1_p_ck)
0x3 : B_0x3
PLL1 via MPUDIV is selected as
system clock (pll1_p_ck / 2
MPUDIV).
End of enumeration elements list.
MPUSRCRDY : MPUSRCRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MPU switch is not ready: no
clock is generated on its output
0x1 : B_0x1
The MPU switch is ready: the clock
switch is selecting the clock given by MPUSRC
field. (default after reset)
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing enables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
IWDG2APBEN : IWDG2APBEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing enables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing disables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
IWDG2APBEN : IWDG2APBEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing disables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
1
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc1 clocks, reading means that the clocks
are enabled for AXI port 1
End of enumeration elements list.
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
2
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc2 clocks, reading means that the clocks
are enabled for AXI port 2
End of enumeration elements list.
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
IWDG1APBEN : IWDG1APBEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing enables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
1
0x1 : B_0x1
Writing disables the AXI port 1
peripheral clocks, reading means that the
peripheral clocks are enabled for AXI port
1
End of enumeration elements list.
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
2
0x1 : B_0x1
Writing disables the AXI port 2
peripheral clocks, reading means that the
peripheral clocks are enabled for AXI port
2
End of enumeration elements list.
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
IWDG1APBEN : IWDG1APBEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing disables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
AXIMCEN : AXIMCEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
AXIMCEN : AXIMCEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled
0x1 : B_0x1
Writing enables the eth_ker_ck
clock, reading means that the eth_ker_ck clock is
enabled
End of enumeration elements list.
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is
disabled
0x1 : B_0x1
Writing enables the transmission
clock, reading means that the transmission clock
is enabled
End of enumeration elements list.
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is
disabled
0x1 : B_0x1
Writing enables the reception clock,
reading means that the reception clock is
enabled
End of enumeration elements list.
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clock is
disabled
0x1 : B_0x1
Writing enables the bus interface
clock, reading means that the bus interface clock
is enabled
End of enumeration elements list.
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled
0x1 : B_0x1
Writing disables the eth_ker_ck
clock, reading means that the eth_ker_ck clock is
enabled
End of enumeration elements list.
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is
disabled
0x1 : B_0x1
Writing disables the transmission
clock, reading means that the transmission clock
is enabled
End of enumeration elements list.
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is
disabled
0x1 : B_0x1
Writing disables the reception
clock, reading means that the reception clock is
enabled
End of enumeration elements list.
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clock is
disabled
0x1 : B_0x1
Writing disables the bus interface
clock, reading means that the bus interface clock
is enabled
End of enumeration elements list.
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AXISSRC : AXISSRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI selected as system clock
(hsi_ck) (default after reset)
0x1 : B_0x1
HSE selected as system clock
(hse_ck)
0x2 : B_0x2
PLL2 selected as system clock
(pll2_p_ck)
End of enumeration elements list.
AXISSRCRDY : AXISSRCRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The AXI sub-system switch is not
ready or in positions higher than : no clock is
generated on its output
0x1 : B_0x1
The AXI sub-system switch is ready:
the clock switch is selecting the clock given by
AXISSRC field. (default after
reset)
End of enumeration elements list.
This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL12SRC : PLL12SRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI selected as PLL clock (hsi_ck)
(default after reset)
0x1 : B_0x1
HSE selected as PLL clock
(hse_ck)
End of enumeration elements list.
PLL12SRCRDY : PLL12SRCRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The PLL12 switch is not ready or in
position : no clock is generated on its
output
0x1 : B_0x1
The PLL12 switch is ready: the clock
switch is selecting the clock given by PLL12SRC
field. (default after reset)
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing enables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled
0x1 : B_0x1
Writing disables the APB clock,
reading means that the APB clock is
enabled
End of enumeration elements list.
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
1
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc1 clocks, reading means that the clocks
are enabled for AXI port 1
End of enumeration elements list.
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
2
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc2 clocks, reading means that the clocks
are enabled for AXI port 2
End of enumeration elements list.
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
1
0x1 : B_0x1
Writing disables the AXI port 1
peripheral clocks, reading means that the
peripheral clocks are enabled for AXI port
1
End of enumeration elements list.
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port
2
0x1 : B_0x1
Writing disables the AXI port 2
peripheral clocks, reading means that the
peripheral clocks are enabled for AXI port
2
End of enumeration elements list.
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled
0x1 : B_0x1
Writing enables the eth_ker_ck
clock, reading means that the eth_ker_ck clock is
enabled
End of enumeration elements list.
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is
disabled
0x1 : B_0x1
Writing enables the transmission
clock, reading means that the transmission clock
is enabled
End of enumeration elements list.
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is
disabled
0x1 : B_0x1
Writing enables the reception clock,
reading means that the reception clock is
enabled
End of enumeration elements list.
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clock is
disabled
0x1 : B_0x1
Writing enables the bus interface
clock, reading means that the bus interface clock
is enabled
End of enumeration elements list.
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled
0x1 : B_0x1
Writing disables the eth_ker_ck
clock, reading means that the eth_ker_ck clock is
enabled
End of enumeration elements list.
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is
disabled
0x1 : B_0x1
Writing disables the transmission
clock, reading means that the transmission clock
is enabled
End of enumeration elements list.
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is
disabled
0x1 : B_0x1
Writing disables the reception
clock, reading means that the reception clock is
enabled
End of enumeration elements list.
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clock is
disabled
0x1 : B_0x1
Writing disables the bus interface
clock, reading means that the bus interface clock
is enabled
End of enumeration elements list.
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to control the MPU clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPUDIV : MPUDIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The MPUDIV is disabled; i.e. no
clock generated
0x1 : B_0x1
The mpuss_ck is equal to pll1_p_ck
divided by 2 (default after reset)
0x2 : B_0x2
The mpuss_ck is equal to pll1_p_ck
divided by 4
0x3 : B_0x3
The mpuss_ck is equal to pll1_p_ck
divided by 8
End of enumeration elements list.
MPUDIVRDY : MPUDIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the AXI Matrix clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AXIDIV : AXIDIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
axiss_ck (default after
reset)
0x1 : B_0x1
axiss_ck / 2
0x2 : B_0x2
axiss_ck / 3
End of enumeration elements list.
AXIDIVRDY : AXIDIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
IWDG2APBLPEN : IWDG2APBLPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSTOP, reading means that the
peripheral clocks are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MPU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
IWDG2APBLPEN : IWDG2APBLPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing disables the clock in CSTOP,
reading means that the clock are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 1 in
CSLEEP
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc1 clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 1 in
CSLEEP
End of enumeration elements list.
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 2 in
CSLEEP
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc2 clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 2 in
CSLEEP
End of enumeration elements list.
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
IWDG1APBLPEN : IWDG1APBLPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSTOP, reading means that the
peripheral clocks are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MPU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 1 in
CSLEEP
0x1 : B_0x1
Writing disables the AXI port 1
peripheral clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 1 in
CSLEEP
End of enumeration elements list.
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 2 in
CSLEEP
0x1 : B_0x1
Writing disables the AXI port 2
peripheral clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 2 in
CSLEEP
End of enumeration elements list.
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
IWDG1APBLPEN : IWDG1APBLPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSTOP, reading means that the
peripheral clocks are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral clock
in CSLEEP, reading means that the clock is
enabled in CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the clock in
CSLEEP, reading means that the clock is enabled
in CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the eth_ker_ck clock
in CSLEEP, reading means that the eth_ker_ck
clock is enabled in CSLEEP
End of enumeration elements list.
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the transmission
clock in CSLEEP, reading means that the
transmission clock is enabled in
CSLEEP
End of enumeration elements list.
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the reception clock
in CSLEEP, reading means that the reception clock
is enabled in CSLEEP
End of enumeration elements list.
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the bus interface
clocks in CSLEEP, reading means that the bus
interface clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the ETH RX and TX kernel clocks are gated in
CSTOP
0x1 : B_0x1
Writing enables the ETH RX and TX
kernel clocks in CSTOP, reading means that the
ETH RX and TX kernel clocks are enabled in
CSTOP
End of enumeration elements list.
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the eth_ker_ck
clock in CSLEEP, reading means that the
eth_ker_ck clock is enabled in
CSLEEP
End of enumeration elements list.
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the transmission
clock in CSLEEP, reading means that the
transmission clock is enabled in
CSLEEP
End of enumeration elements list.
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the reception clock
in CSLEEP, reading means that the reception clock
is enabled in CSLEEP
End of enumeration elements list.
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the bus interface
clocks in CSLEEP, reading means that the bus
interface clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the ETH RX and TX kernel clocks are gated in
CSTOP
0x1 : B_0x1
Writing disabled the ETH RX and TX
kernel clocks in CSTOP, reading means that the
ETH RX and TX kernel clocks are enabled in
CSTOP
End of enumeration elements list.
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MPU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSTOP, reading means that the
peripheral clocks are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the APB clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the APB clock in
CSLEEP, reading means that the APB clock is
enabled in CSLEEP
End of enumeration elements list.
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing disables the clock in CSTOP,
reading means that the clock are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 1 in
CSLEEP
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc1 clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 1 in
CSLEEP
End of enumeration elements list.
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 2 in
CSLEEP
0x1 : B_0x1
Writing enables the pclk5 and
aclk_tzc2 clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 2 in
CSLEEP
End of enumeration elements list.
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSTOP, reading means that the
peripheral clocks are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 1 in
CSLEEP
0x1 : B_0x1
Writing disables the AXI port 1
peripheral clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 1 in
CSLEEP
End of enumeration elements list.
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clocks are disabled for AXI port 2 in
CSLEEP
0x1 : B_0x1
Writing disables the AXI port 2
peripheral clocks in CSLEEP, reading means that
the clocks are enabled for AXI port 2 in
CSLEEP
End of enumeration elements list.
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSTOP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSTOP, reading means that the
peripheral clocks are enabled in
CSTOP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral clock
in CSLEEP, reading means that the clock is
enabled in CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the clock in
CSLEEP, reading means that the clock is enabled
in CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the eth_ker_ck clock
in CSLEEP, reading means that the eth_ker_ck
clock is enabled in CSLEEP
End of enumeration elements list.
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the transmission
clock in CSLEEP, reading means that the
transmission clock is enabled in
CSLEEP
End of enumeration elements list.
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the reception clock
in CSLEEP, reading means that the reception clock
is enabled in CSLEEP
End of enumeration elements list.
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the bus interface
clocks in CSLEEP, reading means that the bus
interface clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the ETH RX and TX kernel clocks are gated in
CSTOP
0x1 : B_0x1
Writing enables the ETH RX and TX
kernel clocks in CSTOP, reading means that the
ETH RX and TX kernel clocks are enabled in
CSTOP
End of enumeration elements list.
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that eth_ker_ck clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the eth_ker_ck
clock in CSLEEP, reading means that the
eth_ker_ck clock is enabled in
CSLEEP
End of enumeration elements list.
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the transmission clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the transmission
clock in CSLEEP, reading means that the
transmission clock is enabled in
CSLEEP
End of enumeration elements list.
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the reception clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the reception clock
in CSLEEP, reading means that the reception clock
is enabled in CSLEEP
End of enumeration elements list.
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the bus interface clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the bus interface
clocks in CSLEEP, reading means that the bus
interface clocks are enabled in
CSLEEP
End of enumeration elements list.
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the ETH RX and TX kernel clocks are gated in
CSTOP
0x1 : B_0x1
Writing disabled the ETH RX and TX
kernel clocks in CSTOP, reading means that the
ETH RX and TX kernel clocks are enabled in
CSTOP
End of enumeration elements list.
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used to control the APB4 clock divider. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB4DIV : APB4DIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
aclk (default after
reset)
0x1 : B_0x1
aclk / 2
0x2 : B_0x2
aclk / 4
0x3 : B_0x3
aclk / 8
End of enumeration elements list.
APB4DIVRDY : APB4DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the APB5 clock divider. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB5DIV : APB5DIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
aclk (default after
reset)
0x1 : B_0x1
aclk / 2
0x2 : B_0x2
aclk / 4
0x3 : B_0x3
aclk / 8
End of enumeration elements list.
APB5DIVRDY : APB5DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .The application running on MPU shall not use this register to define the reset source, the register RCC_MP_RSTSR must be used instead.Please refer to Section1.3.12: Reset Source Identification for details.This register is located into VDD domain, and is reset by por_rst reset. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no POR/PDR reset occurred
0x1 : B_0x1
Writing clears the PORRSTF flag,
reading means that a POR/PDR reset occurred
(default after por_rst reset)
End of enumeration elements list.
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no BOR reset occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the BORRSTF flag,
reading means that a BOR reset
occurred
End of enumeration elements list.
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no PAD reset occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the PADRSTF flag,
reading means that a PAD reset
occurred
End of enumeration elements list.
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no HSE CSS reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the HCSSRSTF flag,
reading means that a HSE CSS reset
occurred
End of enumeration elements list.
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that VDD_CORE is not the origin of the
reset
0x1 : B_0x1
Writing clears the VCORERSTF flag,
reading means that VDD_CORE is the origin of the
reset (default after por_rst reset)
End of enumeration elements list.
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no system reset generated by the MPU
occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the MCURSTF flag,
reading means that a system reset generated by
the MPU occurred
End of enumeration elements list.
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no system reset generated by the MCU
occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the MCURSTF flag,
reading means that a system reset generated by
the MCU occurred
End of enumeration elements list.
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no IWDG1 reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the IWDG1RSTF flag,
reading means that a IWDG1 reset
occurred
End of enumeration elements list.
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no IWDG2 reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the IWDG2RSTF flag,
reading means that a IWDG2 reset
occurred
End of enumeration elements list.
WWDG1RSTF : WWDG1RSTF
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no WWDG1 reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the WWDG1RSTF flag,
reading means that a WWDG1 reset
occurred
End of enumeration elements list.
This register is used by the MPU in order to generate either a MCU reset or a system reset. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSYSRST : MPSYSRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing generate a system reset, see
Figure2.
End of enumeration elements list.
MCURST : MCURST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing generate a reset of the MCU
core, reading means that the block reset is
asserted
End of enumeration elements list.
This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from STANDBY or CSTANDBY.The flags can be cleared by simply writing them to . Please refer to Section1.3.12: Reset Source Identification for details.The register is located in VDD_CORE.If TZEN = , this register can only be modified in secure mode.
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No POR/PDR reset
occurred
0x1 : B_0x1
A POR/PDR reset
occurred
End of enumeration elements list.
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No BOR reset occurred
0x1 : B_0x1
A BOR reset occurred
End of enumeration elements list.
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No PAD reset occurred
0x1 : B_0x1
A PAD reset occurred
End of enumeration elements list.
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No HSE CSS reset
occurred
0x1 : B_0x1
A HSE CSS reset
occurred
End of enumeration elements list.
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDD_CORE is not the origin of the
reset
0x1 : B_0x1
VDD_CORE is the origin of the
reset
End of enumeration elements list.
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No system reset generated by the MPU
occurred
0x1 : B_0x1
A system reset generated by the MPU
occurred
End of enumeration elements list.
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No system reset generated by the MCU
occurred
0x1 : B_0x1
A system reset generated by the MCU
occurred
End of enumeration elements list.
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No IWDG1 reset
occurred
0x1 : B_0x1
An IWDG1 reset
occurred
End of enumeration elements list.
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No IWDG2 reset
occurred
0x1 : B_0x1
An IWDG2 reset
occurred
End of enumeration elements list.
STDBYRSTF : STDBYRSTF
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
System has not been in STANDBY
mode
0x1 : B_0x1
System has been in STANDBY
mode
End of enumeration elements list.
CSTDBYRSTF : CSTDBYRSTF
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MPU has not been in CSTANDBY
mode
0x1 : B_0x1
MPU has been in CSTANDBY
mode
End of enumeration elements list.
SPARE : SPARE
bits : 13 - 15 (3 bit)
access : read-write
This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FZ_IWDG1 : FZ_IWDG1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the IWDG1 clock is not frozen (default after
reset)
0x1 : B_0x1
Writing freeze the IWDG1 clock,
reading means that the IWDG1 clock is
frozen
End of enumeration elements list.
FZ_IWDG2 : FZ_IWDG2
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the IWDG2 clock is not frozen (default after
reset)
0x1 : B_0x1
Writing freeze the IWDG2 clock,
reading means that the IWDG2 clock is
frozen
End of enumeration elements list.
This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FZ_IWDG1 : FZ_IWDG1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the IWDG1 clock is not frozen (default after
reset)
0x1 : B_0x1
Writing unfreeze the IWDG1 clock,
reading means that the IWDG1 clock is
frozen
End of enumeration elements list.
FZ_IWDG2 : FZ_IWDG2
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the IWDG2 clock is not frozen (default after
reset)
0x1 : B_0x1
Writing unfreeze the IWDG2 clock,
reading means that the IWDG2 clock is
frozen
End of enumeration elements list.
This register shall be used by the MPU to control the interrupt source enable. Please refer to Section1.5: RCC Interrupts for more details. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSIRDYIE
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI ready interrupt disabled
(default after reset)
0x1 : B_0x1
LSI ready interrupt
enabled
End of enumeration elements list.
LSERDYIE : LSERDYIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE ready interrupt disabled
(default after reset)
0x1 : B_0x1
LSE ready interrupt
enabled
End of enumeration elements list.
HSIRDYIE : HSIRDYIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI ready interrupt disabled
(default after reset)
0x1 : B_0x1
HSI ready interrupt
enabled
End of enumeration elements list.
HSERDYIE : HSERDYIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE ready interrupt disabled
(default after reset)
0x1 : B_0x1
HSE ready interrupt
enabled
End of enumeration elements list.
CSIRDYIE : CSIRDYIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CSI ready interrupt disabled
(default after reset)
0x1 : B_0x1
CSI ready interrupt
enabled
End of enumeration elements list.
PLL1DYIE : PLL1DYIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL1 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL1 lock interrupt
enabled
End of enumeration elements list.
PLL2DYIE : PLL2DYIE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL2 lock interrupt
enabled
End of enumeration elements list.
PLL3DYIE : PLL3DYIE
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL3 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL3 lock interrupt
enabled
End of enumeration elements list.
PLL4DYIE : PLL4DYIE
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL4 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL4 lock interrupt
enabled
End of enumeration elements list.
LSECSSIE : LSECSSIE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE CSS interrupt disabled (default
after reset)
0x1 : B_0x1
LSE CSS interrupt
enabled
End of enumeration elements list.
WKUPIE : WKUPIE
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wake-up interrupt disabled (default
after reset)
0x1 : B_0x1
Wake-up interrupt
enabled
End of enumeration elements list.
This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Please refer to Section1.5: RCC Interrupts for more details. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSIRDYF
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the LSI (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
LSI, writing clears this flag
End of enumeration elements list.
LSERDYF : LSERDYF
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the LSE (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
LSE, writing clears this flag
End of enumeration elements list.
HSIRDYF : HSIRDYF
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the HSI (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
HSI, writing clears this flag
End of enumeration elements list.
HSERDYF : HSERDYF
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the HSE (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
HSE, writing clears this flag
End of enumeration elements list.
CSIRDYF : CSIRDYF
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the CSI (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
CSI, writing clears this flag
End of enumeration elements list.
PLL1DYF : PLL1DYF
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL1 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL1
lock, writing clears this flag
End of enumeration elements list.
PLL2DYF : PLL2DYF
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL2 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL2
lock, writing clears this flag
End of enumeration elements list.
PLL3DYF : PLL3DYF
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL3 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL3
lock, writing clears this flag
End of enumeration elements list.
PLL4DYF : PLL4DYF
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL4 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL4
lock, writing clears this flag
End of enumeration elements list.
LSECSSF : LSECSSF
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No failure detected on the external
32 kHz oscillator (default after
reset)
0x1 : B_0x1
A failure is detected on the
external 32 kHz oscillator, writing clears this
flag
End of enumeration elements list.
WKUPF : WKUPF
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No wake-up interrupt pending
(default after reset)
0x1 : B_0x1
Wake-up interrupt pending, writing
clears this flag
End of enumeration elements list.
This register is used to program the delay between the moment where the system exits from STOP and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRLP_DLY : PWRLP_DLY
bits : 0 - 21 (22 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The PWR_LP delay is bypassed
(default after reset)
0x1 : B_0x1
A PWR_LP delay of one period of HSI
(at 64 MHz) is observed
0x3FFFFF : B_0x3FFFFF
A PWR_LP delay of about 65.5
milliseconds is observed
End of enumeration elements list.
MCTMPSKP : MCTMPSKP
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The clock restore sequence of the
MCU waits for the PWR_LP delay before activating
power consuming elements (default after
reset)
0x1 : B_0x1
The clock restore sequence of the
MCU runs the PWR_LP delay but did not wait for
the delay to elapse before activating power
consuming elements
End of enumeration elements list.
This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCDIV : RTCDIV
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE (default after
reset)
0x1 : B_0x1
HSE/2
0x2 : B_0x2
HSE/3
0x3 : B_0x3
HSE/4
0x3E : B_0x3E
HSE/63
0x3F : B_0x3F
HSE/64
End of enumeration elements list.
This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCUSSRC : MCUSSRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI selected as system clock
(hsi_ck) (default after reset)
0x1 : B_0x1
HSE selected as system clock
(hse_ck)
0x2 : B_0x2
CSI selected as system clock
(csi_ck)
0x3 : B_0x3
PLL3 selected as system clock
(pll3_p_ck)
End of enumeration elements list.
MCUSSRCRDY : MCUSSRCRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The MCU sub-system switch is not
ready or in positions higher than : no clock is
generated on its output
0x1 : B_0x1
The MCU sub-system switch is ready:
the clock switch is selecting the clock given by
MCUSSRC field. (default after
reset)
End of enumeration elements list.
This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL1 OFF (default after
reset)
0x1 : B_0x1
PLL1 is ON, and ref1_ck is provided
to the PLL1
End of enumeration elements list.
PLL1RDY : PLL1RDY
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL1 unlocked (default after
reset)
0x1 : B_0x1
PLL1 locked
End of enumeration elements list.
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock Spreading Generator disabled
(default after reset)
0x1 : B_0x1
Clock Spreading Generator
enabled
End of enumeration elements list.
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_p_ck output is disabled
(default after reset)
0x1 : B_0x1
pll1_p_ck output is
enabled
End of enumeration elements list.
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_q_ck output is disabled
(default after reset)
0x1 : B_0x1
pll1_q_ck output is
enabled
End of enumeration elements list.
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_r_ck output is disabled
(default after reset)
0x1 : B_0x1
pll1_r_ck output is
enabled
End of enumeration elements list.
This register is used to select the clock generated on MCO1 output.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCO1SEL : MCO1SEL
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI clock selected (hsi_ck) (default
after reset)
0x1 : B_0x1
HSE clock selected
(hse_ck)
0x2 : B_0x2
CSI clock selected
(csi_ck)
0x3 : B_0x3
LSI clock selected
(lsi_ck)
0x4 : B_0x4
LSE oscillator clock selected
(lse_ck)
End of enumeration elements list.
MCO1DIV : MCO1DIV
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass (default after
reset)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 3
0xF : B_0xF
division by 16
End of enumeration elements list.
MCO1ON : MCO1ON
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The MCO1 output is
disabled
0x1 : B_0x1
The MCO1 output is
enabled
End of enumeration elements list.
This register is used to select the clock generated on MCO2 output.
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCO2SEL : MCO2SEL
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MPU clock selected (mpuss_ck)
(default after reset)
0x1 : B_0x1
AXI clock selected
(axiss_ck)
0x2 : B_0x2
MCU clock selected
(mcuss_ck)
0x3 : B_0x3
PLL4 clock selected
(pll4_p_ck)
0x4 : B_0x4
HSE clock selected
(hse_ck)
0x5 : B_0x5
HSI clock selected
(hsi_ck)
End of enumeration elements list.
MCO2DIV : MCO2DIV
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass (default after
reset)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 3
0xF : B_0xF
division by 16
End of enumeration elements list.
MCO2ON : MCO2ON
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The MCO2 output is
disabled
0x1 : B_0x1
The MCO2 output is
enabled
End of enumeration elements list.
This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSIRDY : HSIRDY
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
HSI clock is not ready (default
after reset)
0x1 : B_0x1
HSI clock is ready
End of enumeration elements list.
HSIDIVRDY : HSIDIVRDY
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
the new division ratio is not yet
propagated to hsi_ck (hsi_ker_ck) (default after
reset)
0x1 : B_0x1
the hsi_ck (hsi_ker_ck) clock
frequency reflects the new HSIDIV
value
End of enumeration elements list.
CSIRDY : CSIRDY
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
CSI clock is not ready (default
after reset)
0x1 : B_0x1
CSI clock is ready
End of enumeration elements list.
HSERDY : HSERDY
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
HSE clock is not ready (default
after reset)
0x1 : B_0x1
HSE clock is ready
End of enumeration elements list.
MPUCKRDY : MPUCKRDY
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
mpuss_ck clock is not available
(default after reset)
0x1 : B_0x1
mpuss_ck clock is
available
End of enumeration elements list.
AXICKRDY : AXICKRDY
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
axiss_ck clock is not available
(default after reset)
0x1 : B_0x1
axiss_ck clock is
available
End of enumeration elements list.
CKREST : CKREST
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The clock restore process is not
on-going (default after reset)
0x1 : B_0x1
The clock restore process is
on-going
End of enumeration elements list.
This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACEDIV : TRACEDIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
aclk
0x1 : B_0x1
aclk / 2 (default after
reset)
0x2 : B_0x2
aclk / 4
0x3 : B_0x3
aclk / 8
End of enumeration elements list.
DBGCKEN : DBGCKEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The enabling of the clock for the
debug function is controlled by cdbgwrupreq
signal from DAP. (default after
reset)
0x1 : B_0x1
The clock for the debug function is
enabled
End of enumeration elements list.
TRACECKEN : TRACECKEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The clock for the trace function is
disabled (default after reset)
0x1 : B_0x1
The clock for the trace function is
enabled
End of enumeration elements list.
DBGRST : DBGRST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The trace and debug parts are not
reset. (default after reset)
0x1 : B_0x1
The trace and debug parts are under
reset.
End of enumeration elements list.
This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL3SRC : PLL3SRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI selected as PLL clock (hsi_ck)
(default after reset)
0x1 : B_0x1
HSE selected as PLL clock
(hse_ck)
0x2 : B_0x2
CSI selected as PLL clock
(csi_ck)
0x3 : B_0x3
No clock send to DIVMx divider and
PLLs
End of enumeration elements list.
PLL3SRCRDY : PLL3SRCRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The PLL3 switch is not ready or in
position : no clock is generated on its
output
0x1 : B_0x1
The PLL3 switch is ready: the clock
switch is selecting the clock given by PLL3SRC
field. (default after reset)
End of enumeration elements list.
This register is used to select the reference clock for PLL4.
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL4SRC : PLL4SRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI selected as PLL clock (hsi_ck)
(default after reset)
0x1 : B_0x1
HSE selected as PLL clock
(hse_ck)
0x2 : B_0x2
CSI selected as PLL clock
(csi_ck)
0x3 : B_0x3
Signal I2S_CKIN used as reference
clock
End of enumeration elements list.
PLL4SRCRDY : PLL4SRCRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The PLL4 switch is not ready or in
position : no clock is generated on its
output
0x1 : B_0x1
The PLL4 switch is ready: the clock
switch is selecting the clock given by PLL4SRC
field. (default after reset)
End of enumeration elements list.
This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information.
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMG1PRE : TIMG1PRE
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The Timers kernel clock is equal to
mlhclk if APB1DIV is corresponding to a division
by 1 or 2, else it is equal to 2 x Fpclk1
(default after reset)
0x1 : B_0x1
The Timers kernel clock is equal to
mlhclk if APB1DIV is corresponding to division by
1, 2 or 4, else it is equal to 4 x
Fpclk1
End of enumeration elements list.
TIMG1PRERDY : TIMG1PRERDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information.
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMG2PRE : TIMG2PRE
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The Timers kernel clock is equal to
mlhclk if APB2DIV is corresponding to a division
by 1 or 2, else it is equal to 2 x Fpclk2
(default after reset)
0x1 : B_0x1
The Timers kernel clock is equal to
mlhclk if APB2DIV is corresponding to division by
1, 2 or 4, else it is equal to 4 x
Fpclk2
End of enumeration elements list.
TIMG2PRERDY : TIMG2PRERDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the MCU sub-system clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCUDIV : MCUDIV
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
mcuss_ck not divided (default after
reset)
0x1 : B_0x1
mcuss_ck divided by 2
0x2 : B_0x2
mcuss_ck divided by 4
0x3 : B_0x3
mcuss_ck divided by 8
0x4 : B_0x4
mcuss_ck divided by 16
0x5 : B_0x5
mcuss_ck divided by 32
0x6 : B_0x6
mcuss_ck divided by 64
0x7 : B_0x7
mcuss_ck divided by
128
0x8 : B_0x8
mcuss_ck divided by
256
End of enumeration elements list.
MCUDIVRDY : MCUDIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the APB1 clock prescaler. Please refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB1DIV : APB1DIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
mlhclk (default after
reset)
0x1 : B_0x1
mlhclk / 2
0x2 : B_0x2
mlhclk / 4
0x3 : B_0x3
mlhclk / 8
0x4 : B_0x4
mlhclk / 16
End of enumeration elements list.
APB1DIVRDY : APB1DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the APB2 clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information.
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB2DIV : APB2DIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
mlhclk (default after
reset)
0x1 : B_0x1
mlhclk / 2
0x2 : B_0x2
mlhclk / 4
0x3 : B_0x3
mlhclk / 8
0x4 : B_0x4
mlhclk / 16
End of enumeration elements list.
APB2DIVRDY : APB2DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to control the APB3 clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information.
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB3DIV : APB3DIV
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hclk (default after
reset)
0x1 : B_0x1
hclk / 2
0x2 : B_0x2
hclk / 4
0x3 : B_0x3
hclk / 8
End of enumeration elements list.
APB3DIVRDY : APB3DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The new division factor is not yet
taken into account.
0x1 : B_0x1
The new division factor is taken
into account. (default after reset)
End of enumeration elements list.
This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x18 : B_0x18
Division ratio is 25
0x19 : B_0x19
Division ratio is 26
0x31 : B_0x31
Division ratio is 50 (default after
reset)
0x63 : B_0x63
Division ratio is 100
End of enumeration elements list.
DIVM1 : DIVM1
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass
0x1 : B_0x1
division by 2 (default after
reset)
0x2 : B_0x2
division by 3
0x3F : B_0x3F
division by 64
End of enumeration elements list.
This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_p_ck = fout1_ck (default after
reset)
0x1 : B_0x1
pll1_p_ck = fout1_ck /
2
0x2 : B_0x2
pll1_p_ck = fout1_ck /
3
0x7F : B_0x7F
pll1_p_ck = fout1_ck /
128
End of enumeration elements list.
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_q_ck = fout1_ck
0x1 : B_0x1
pll1_q_ck = fout1_ck / 2 (default
after reset)
0x2 : B_0x2
pll1_q_ck = fout1_ck /
3
0x7F : B_0x7F
pll1_q_ck = fout1_ck /
128
End of enumeration elements list.
DIVR : DIVR
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_r_ck = fout1_ck
0x1 : B_0x1
pll1_r_ck = fout1_ck / 2 (default
after reset)
0x2 : B_0x2
pll1_r_ck = fout1_ck /
3
0x7F : B_0x7F
pll1_r_ck = fout1_ck /
128
End of enumeration elements list.
This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL3 OFF (default after
reset)
0x1 : B_0x1
PLL3 ON, and ref3_ck is provided to
the PLL3
End of enumeration elements list.
PLL3RDY : PLL3RDY
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL3 unlocked (default after
reset)
0x1 : B_0x1
PLL3 locked
End of enumeration elements list.
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock Spreading Generator disabled
(default after reset)
0x1 : B_0x1
Clock Spreading Generator
enabled
End of enumeration elements list.
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_p_ck output is disabled
(default after reset)
0x1 : B_0x1
pll3_p_ck output is
enabled
End of enumeration elements list.
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_q_ck output is disabled
(default after reset)
0x1 : B_0x1
pll3_q_ck output is
enabled
End of enumeration elements list.
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_r_ck output is disabled
(default after reset)
0x1 : B_0x1
pll3_r_ck output is
enabled
End of enumeration elements list.
This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x18 : B_0x18
Division ratio is 25
0x19 : B_0x19
Division ratio is 26
0x1A : B_0x1A
Division ratio is 27
0x31 : B_0x31
Division ratio is 50 (default after
reset)
0xC7 : B_0xC7
Division ratio is 200
End of enumeration elements list.
DIVM3 : DIVM3
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass
0x1 : B_0x1
division by 2 (default after
reset)
0x2 : B_0x2
division by 3
0x3F : B_0x3F
division by 64
End of enumeration elements list.
IFRGE : IFRGE
bits : 24 - 25 (2 bit)
access : read-write
This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_p_ck = vco3_ck
0x1 : B_0x1
pll3_p_ck = vco3_ck / 2 (default
after reset)
0x2 : B_0x2
pll3_p_ck = vco3_ck /
3
0x7F : B_0x7F
pll3_p_ck = vco3_ck /
128
End of enumeration elements list.
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_q_ck = vco3_ck
0x1 : B_0x1
pll3_q_ck = vco3_ck / 2 (default
after reset)
0x2 : B_0x2
pll3_q_ck = vco3_ck /
3
0x7F : B_0x7F
pll3_q_ck = vco3_ck /
128
End of enumeration elements list.
DIVR : DIVR
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_r_ck = vco3_ck
0x1 : B_0x1
pll3_r_ck = vco3_ck / 2 (default
after reset)
0x2 : B_0x2
pll3_r_ck = vco3_ck /
3
0x7F : B_0x7F
pll3_r_ck = vco3_ck /
128
End of enumeration elements list.
This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
access : read-write
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
access : read-write
This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
access : read-write
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Center-spread modulation selected
(default after reset)
0x1 : B_0x1
Down-spread modulation
selected
End of enumeration elements list.
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
access : read-write
This register is used to control the PLL4.
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL4 OFF (default after
reset)
0x1 : B_0x1
PLL4 ON, and ref4_ck is provided to
the PLL4
End of enumeration elements list.
PLL4RDY : PLL4RDY
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL4 unlocked (default after
reset)
0x1 : B_0x1
PLL4 locked
End of enumeration elements list.
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock Spreading Generator disabled
(default after reset)
0x1 : B_0x1
Clock Spreading Generator
enabled
End of enumeration elements list.
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_p_ck output is disabled
(default after reset)
0x1 : B_0x1
pll4_p_ck output is
enabled
End of enumeration elements list.
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck output is disabled
(default after reset)
0x1 : B_0x1
pll4_q_ck output is
enabled
End of enumeration elements list.
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_r_ck output is disabled
(default after reset)
0x1 : B_0x1
pll4_r_ck output is
enabled
End of enumeration elements list.
This register is used to configure the PLL4.
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x18 : B_0x18
Division ratio is 25
0x19 : B_0x19
Division ratio is 26
0x1A : B_0x1A
Division ratio is 27
0x31 : B_0x31
Division ratio is 50 (default after
reset)
0xC7 : B_0xC7
Division ratio is 200
End of enumeration elements list.
DIVM4 : DIVM4
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass
0x1 : B_0x1
division by 2 (default after
reset)
0x2 : B_0x2
division by 3
0x3F : B_0x3F
division by 64
End of enumeration elements list.
IFRGE : IFRGE
bits : 24 - 25 (2 bit)
access : read-write
This register is used to configure the PLL4.
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_p_ck = vco4_ck
0x1 : B_0x1
pll4_p_ck = vco4_ck / 2 (default
after reset)
0x2 : B_0x2
pll4_p_ck = vco4_ck /
3
0x7F : B_0x7F
pll4_p_ck = vco4_ck /
128
End of enumeration elements list.
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck = vco4_ck
0x1 : B_0x1
pll4_q_ck = vco4_ck / 2 (default
after reset)
0x2 : B_0x2
pll4_q_ck = vco4_ck /
3
0x7F : B_0x7F
pll4_q_ck = vco4_ck /
128
End of enumeration elements list.
DIVR : DIVR
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_r_ck = vco4_ck
0x1 : B_0x1
pll4_r_ck = vco4_ck / 2 (default
after reset)
0x2 : B_0x2
pll4_r_ck = vco4_ck /
3
0x7F : B_0x7F
pll4_r_ck = vco4_ck /
128
End of enumeration elements list.
This register is used to fine-tune the frequency of the PLL4 VCO.
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
access : read-write
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
access : read-write
This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
access : read-write
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Center-spread modulation selected
(default after reset)
0x1 : B_0x1
Down-spread modulation
selected
End of enumeration elements list.
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
access : read-write
This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
access : read-write
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
access : read-write
This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C12SRC : I2C12SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk1 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C35SRC : I2C35SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk1 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI1SRC : SAI1SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
I2S_CKIN clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI2SRC : SAI2SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
I2S_CKIN clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
spdif_ck_symb clock from SPDIFRX
selected as kernel peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI3SRC : SAI3SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
I2S_CKIN clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI4SRC : SAI4SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
I2S_CKIN clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1SRC : SPI1SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_p_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
I2S_CKIN clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI23SRC : SPI23SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_p_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
I2S_CKIN clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI45SRC : SPI45SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk2 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
hse_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART6SRC : UART6SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk2 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
hse_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART24SRC : UART24SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk1 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
hse_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART35SRC : UART35SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk1 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
hse_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART78SRC : UART78SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk1 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
hse_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMMC12SRC : SDMMC12SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hclk6 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll4_p_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
hsi_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMMC3SRC : SDMMC3SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hclk2 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll4_p_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
hsi_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHSRC : ETHSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_p_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
ETHPTPDIV : ETHPTPDIV
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass (default after
reset)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 3
0xF : B_0xF
division by 16
End of enumeration elements list.
This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
access : read-write
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Center-spread modulation selected
(default after reset)
0x1 : B_0x1
Down-spread modulation
selected
End of enumeration elements list.
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
access : read-write
This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPISRC : QSPISRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
aclk clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll4_p_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMCSRC : FMCSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
aclk clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll4_p_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDCANSRC : FDCANSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hse_ker_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll4_q_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDIFSRC : SPDIFSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_p_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the CEC-HDMI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECSRC : CECSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
lse_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
lsi_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
csi_ker_ck/122 clock selected as
kernel peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG. It also controls the pre-divider for the reference clock for the USBPHY. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBPHYSRC : USBPHYSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hse_ker_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hse_ker_ck/2 clock selected as
kernel peripheral clock
End of enumeration elements list.
USBOSRC : USBOSRC
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_r_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
clock provided by the USB PHY
(rcc_ck_usbo_48m) selected as kernel peripheral
clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the RNG2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time.
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNG2SRC : RNG2SRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
csi_ker_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
lse_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
lsi_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the DSI block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSISRC : DSISRC
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DSI clock from PHY is selected as
DSI byte lane clock (default after
reset)
0x1 : B_0x1
pll4_p_ck clock selected as DSI byte
lane clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the ADC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCSRC : ADCSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll4_q_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM45SRC : LPTIM45SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk3 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_p_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll3_q_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
lse_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
lsi_ck clock selected as kernel
peripheral clock
0x5 : B_0x5
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM23SRC : LPTIM23SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk3 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
per_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
lse_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
lsi_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the LPTIM1 block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM1SRC : LPTIM1SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk1 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_p_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
pll3_q_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
lse_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
lsi_ck clock selected as kernel
peripheral clock
0x5 : B_0x5
per_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 OFF (default after
reset)
0x1 : B_0x1
PLL2 ON, and ref2_ck is provided to
the PLL2
End of enumeration elements list.
PLL2RDY : PLL2RDY
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL2 unlocked (default after
reset)
0x1 : B_0x1
PLL2 locked
End of enumeration elements list.
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock Spreading Generator disabled
(default after reset)
0x1 : B_0x1
Clock Spreading Generator
enabled
End of enumeration elements list.
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_p_ck output is disabled
(default after reset)
0x1 : B_0x1
pll2_p_ck output is
enabled
End of enumeration elements list.
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_q_ck output is disabled
(default after reset)
0x1 : B_0x1
pll2_q_ck output is
enabled
End of enumeration elements list.
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_r_ck output is disabled
(default after reset)
0x1 : B_0x1
pll2_r_ck output is
enabled
End of enumeration elements list.
This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x18 : B_0x18
Division ratio is 25
0x19 : B_0x19
Division ratio is 26
0x31 : B_0x31
Division ratio is 50
0x63 : B_0x63
Division ratio is 100 (default after
reset)
End of enumeration elements list.
DIVM2 : DIVM2
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x0 : B_0x0
bypass
0x1 : B_0x1
division by 2 (default after
reset)
0x2 : B_0x2
division by 3
0x3F : B_0x3F
division by 64
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM3RST : TIM3RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM4RST : TIM4RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM5RST : TIM5RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM6RST : TIM6RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM7RST : TIM7RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM12RST : TIM12RST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM13RST : TIM13RST
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM14RST : TIM14RST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM1RST : LPTIM1RST
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI2RST : SPI2RST
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI3RST : SPI3RST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART2RST : USART2RST
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART3RST : USART3RST
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART4RST : UART4RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART5RST : UART5RST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART7RST : UART7RST
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART8RST : UART8RST
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C1RST : I2C1RST
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C2RST : I2C2RST
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C3RST : I2C3RST
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C5RST : I2C5RST
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPDIFRST : SPDIFRST
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CECRST : CECRST
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DAC12RST : DAC12RST
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
MDIOSRST : MDIOSRST
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM3RST : TIM3RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM4RST : TIM4RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM5RST : TIM5RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM6RST : TIM6RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM7RST : TIM7RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM12RST : TIM12RST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM13RST : TIM13RST
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM14RST : TIM14RST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM1RST : LPTIM1RST
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI2RST : SPI2RST
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI3RST : SPI3RST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART2RST : USART2RST
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART3RST : USART3RST
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART4RST : UART4RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART5RST : UART5RST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART7RST : UART7RST
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
UART8RST : UART8RST
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C1RST : I2C1RST
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C2RST : I2C2RST
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C3RST : I2C3RST
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
I2C5RST : I2C5RST
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPDIFRST : SPDIFRST
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CECRST : CECRST
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DAC12RST : DAC12RST
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
MDIOSRST : MDIOSRST
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing release the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1RST : TIM1RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM8RST : TIM8RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM15RST : TIM15RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM16RST : TIM16RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM17RST : TIM17RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI1RST : SPI1RST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI4RST : SPI4RST
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI5RST : SPI5RST
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART6RST : USART6RST
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI1RST : SAI1RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI2RST : SAI2RST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI3RST : SAI3RST
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DFSDMRST : DFSDMRST
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
FDCANRST : FDCANRST
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x98C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1RST : TIM1RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM8RST : TIM8RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM15RST : TIM15RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM16RST : TIM16RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TIM17RST : TIM17RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI1RST : SPI1RST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI4RST : SPI4RST
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SPI5RST : SPI5RST
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USART6RST : USART6RST
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI1RST : SAI1RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI2RST : SAI2RST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI3RST : SAI3RST
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DFSDMRST : DFSDMRST
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
FDCANRST : FDCANRST
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2RST : LPTIM2RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM3RST : LPTIM3RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM4RST : LPTIM4RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM5RST : LPTIM5RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI4RST : SAI4RST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SYSCFGRST : SYSCFGRST
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
VREFRST : VREFRST
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TMPSENSRST : TMPSENSRST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
PMBCTRLRST : PMBCTRLRST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2RST : LPTIM2RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM3RST : LPTIM3RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM4RST : LPTIM4RST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
LPTIM5RST : LPTIM5RST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SAI4RST : SAI4RST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SYSCFGRST : SYSCFGRST
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
VREFRST : VREFRST
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
TMPSENSRST : TMPSENSRST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
PMBCTRLRST : PMBCTRLRST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1RST : DMA1RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DMA2RST : DMA2RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DMAMUXRST : DMAMUXRST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
ADC12RST : ADC12RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USBORST : USBORST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SDMMC3RST : SDMMC3RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1RST : DMA1RST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DMA2RST : DMA2RST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
DMAMUXRST : DMAMUXRST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
ADC12RST : ADC12RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
USBORST : USBORST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
SDMMC3RST : SDMMC3RST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIRST : DCMIRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRYP2RST : CRYP2RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
HASH2RST : HASH2RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
RNG2RST : RNG2RST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRC2RST : CRC2RST
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
HSEMRST : HSEMRST
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
IPCCRST : IPCCRST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIRST : DCMIRST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRYP2RST : CRYP2RST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
HASH2RST : HASH2RST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
RNG2RST : RNG2RST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
CRC2RST : CRC2RST
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
HSEMRST : HSEMRST
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
IPCCRST : IPCCRST
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : GPIOARST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOBRST : GPIOBRST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOCRST : GPIOCRST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIODRST : GPIODRST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOERST : GPIOERST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOFRST : GPIOFRST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOGRST : GPIOGRST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOHRST : GPIOHRST
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOIRST : GPIOIRST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOJRST : GPIOJRST
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOKRST : GPIOKRST
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing asserts the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : GPIOARST
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOBRST : GPIOBRST
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOCRST : GPIOCRST
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIODRST : GPIODRST
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOERST : GPIOERST
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOFRST : GPIOFRST
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOGRST : GPIOGRST
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOHRST : GPIOHRST
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOIRST : GPIOIRST
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOJRST : GPIOJRST
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
GPIOKRST : GPIOKRST
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the block reset is released
0x1 : B_0x1
Writing releases the block reset,
reading means that the block reset is
asserted
End of enumeration elements list.
This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_p_ck = fout2_ck
0x1 : B_0x1
pll2_p_ck = fout2_ck / 2 (default
after reset)
0x2 : B_0x2
pll2_p_ck = fout2_ck /
3
0x7F : B_0x7F
pll2_p_ck = fout2_ck /
128
End of enumeration elements list.
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_q_ck = fout2_ck
0x1 : B_0x1
pll2_q_ck = fout2_ck / 2 (default
after reset)
0x2 : B_0x2
pll2_q_ck = fout2_ck /
3
0x7F : B_0x7F
pll2_q_ck = fout2_ck /
128
End of enumeration elements list.
DIVR : DIVR
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_r_ck = fout2_ck
0x1 : B_0x1
pll2_r_ck = fout2_ck / 2 (default
after reset)
0x2 : B_0x2
pll2_r_ck = fout2_ck /
3
0x7F : B_0x7F
pll2_r_ck = fout2_ck /
128
End of enumeration elements list.
This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
access : read-write
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
access : read-write
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective value of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CECEN : CECEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CECEN : CECEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TMPSENSEN : TMPSENSEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
PMBCTRLEN : PMBCTRLEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TMPSENSEN : TMPSENSEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
PMBCTRLEN : PMBCTRLEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory is not allocated by the
MPU
0x1 : B_0x1
Writing allocates the memory to the
MPU, reading means that the memory is allocated
to the MPU.
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory is not allocated by the
MPU
0x1 : B_0x1
Writing deallocates the memory to
the MPU, reading means that the memory is
allocated to the MPU.
End of enumeration elements list.
This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
access : read-write
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Dithering noise injection enabled
(default after reset)
0x1 : B_0x1
Dithering noise injection
disabled
End of enumeration elements list.
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Center-spread modulation selected
(default after reset)
0x1 : B_0x1
Down-spread modulation
selected
End of enumeration elements list.
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
access : read-write
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CECEN : CECEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
WWDG1EN : WWDG1EN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CECEN : CECEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TMPSENSEN : TMPSENSEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
PMBCTRLEN : PMBCTRLEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
TMPSENSEN : TMPSENSEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
PMBCTRLEN : PMBCTRLEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing enables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are
disabled
0x1 : B_0x1
Writing disables the peripheral
clocks, reading means that the peripheral clocks
are enabled
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMEN : SYSRAMEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory is not allocated by the
MCU
0x1 : B_0x1
Writing allocates the memory to the
MCU, reading means that the memory is allocated
to the MCU.
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMEN : SYSRAMEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory is not allocated by the
MCU
0x1 : B_0x1
Writing deallocates the memory to
the MCU, reading means that the memory is
allocated to the MCU.
End of enumeration elements list.
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xAB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory is not allocated by the
MCU
0x1 : B_0x1
Writing allocates the memory to the
MCU, reading means that the memory is allocated
to the MCU.
End of enumeration elements list.
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory is not allocated by the
MCU
0x1 : B_0x1
Writing deallocates the memory to
the MCU, reading means that the memory is
allocated to the MCU.
End of enumeration elements list.
This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MPU in order to clear the PERxLPEN bits of the corresponding peripherals located into the APB1 bus. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TMPSENSLPEN : TMPSENSLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
PMBCTRLLPEN : PMBCTRLLPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TMPSENSLPEN : TMPSENSLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
PMBCTRLLPEN : PMBCTRLLPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface clock is enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP
End of enumeration elements list.
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP.
End of enumeration elements list.
SRAM3LPEN : SRAM3LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP
End of enumeration elements list.
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
SRAM3LPEN : SRAM3LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
WWDG1LPEN : WWDG1LPEN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding peripherals located into the APB1 bus. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
WWDG1LPEN : WWDG1LPEN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TMPSENSLPEN : TMPSENSLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
PMBCTRLLPEN : PMBCTRLLPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
TMPSENSLPEN : TMPSENSLPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
PMBCTRLLPEN : PMBCTRLLPEN
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing enables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the peripheral clocks are disabled in
CSLEEP
0x1 : B_0x1
Writing disables the peripheral
clocks in CSLEEP, reading means that the
peripheral clocks are enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface clock is enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP
End of enumeration elements list.
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP.
End of enumeration elements list.
SRAM3LPEN : SRAM3LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP
End of enumeration elements list.
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing enables the memory interface
clock in CSLEEP, reading means that the memory
interface is enabled in CSLEEP
End of enumeration elements list.
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0xBBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
SRAM3LPEN : SRAM3LPEN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that the memory interface clock is disabled in
CSLEEP
0x1 : B_0x1
Writing disables the memory
interface clock in CSLEEP, reading means that the
memory interface is enabled in
CSLEEP
End of enumeration elements list.
This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSION : HSION
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set the HSION bit
End of enumeration elements list.
HSIKERON : HSIKERON
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set the HSIKERON bit
End of enumeration elements list.
CSION : CSION
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set the CSION bit
End of enumeration elements list.
CSIKERON : CSIKERON
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set the CSIKERON bit
End of enumeration elements list.
DIGBYP : DIGBYP
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set DIGBYP bit (digital
bypass)
End of enumeration elements list.
HSEON : HSEON
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set HSEON bit
End of enumeration elements list.
HSEKERON : HSEKERON
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set the HSEKERON bit
End of enumeration elements list.
HSEBYP : HSEBYP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Set the HSEBYP bit
End of enumeration elements list.
HSECSSON : HSECSSON
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Reading means that the Clock
Security System on HSE is OFF (default after
reset)
0x1 : B_0x1
Writing enables the Clock Security
System on HSE, reading means that the Clock
Security System on HSE is ON
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the I2C4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C46SRC : I2C46SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk5 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used by the MCU to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Please refer to Section1.3.12: Reset Source Identification for details.This register is located into VDD domain, and is reset by por_rst reset.
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no POR/PDR reset occurred
0x1 : B_0x1
Writing clears the PORRSTF flag,
reading means that a POR/PDR reset occurred
(default after por_rst reset)
End of enumeration elements list.
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no BOR reset occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the BORRSTF flag,
reading means that a BOR reset
occurred
End of enumeration elements list.
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no PAD reset occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the PADRSTF flag,
reading means that a PAD reset
occurred
End of enumeration elements list.
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no HSE CSS reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the HCSSRSTF flag,
reading means that a HSE CSS reset
occurred
End of enumeration elements list.
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that VDD_CORE is not the origin of the
reset
0x1 : B_0x1
Writing clears the VCORERSTF flag,
reading means that VDD_CORE is the origin of the
reset (default after por_rst reset)
End of enumeration elements list.
MCURSTF : MCURSTF
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no MCU reset occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the MCURSTF flag,
reading means that a MCU reset
occurred
End of enumeration elements list.
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no system reset generated by the MPU
occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the MCURSTF flag,
reading means that a system reset generated by
the MPU occurred
End of enumeration elements list.
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no system reset generated by the MCU
occurred (default after por_rst
reset)
0x1 : B_0x1
Writing clears the MCURSTF flag,
reading means that a system reset generated by
the MCU occurred
End of enumeration elements list.
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no IWDG1 reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the IWDG1RSTF flag,
reading means that a IWDG1 reset
occurred
End of enumeration elements list.
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no IWDG2 reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the IWDG2RSTF flag,
reading means that a IWDG2 reset
occurred
End of enumeration elements list.
WWDG1RSTF : WWDG1RSTF
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing has no effect, reading means
that no WWDG1 reset occurred (default after
por_rst reset)
0x1 : B_0x1
Writing clears the WWDG1RSTF flag,
reading means that a WWDG1 reset
occurred
End of enumeration elements list.
This register shall be used by the MCU to control the interrupt source enable. Please refer to Section1.5: RCC Interrupts for more details.
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSIRDYIE
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI ready interrupt disabled
(default after reset)
0x1 : B_0x1
LSI ready interrupt
enabled
End of enumeration elements list.
LSERDYIE : LSERDYIE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE ready interrupt disabled
(default after reset)
0x1 : B_0x1
LSE ready interrupt
enabled
End of enumeration elements list.
HSIRDYIE : HSIRDYIE
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI ready interrupt disabled
(default after reset)
0x1 : B_0x1
HSI ready interrupt
enabled
End of enumeration elements list.
HSERDYIE : HSERDYIE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE ready interrupt disabled
(default after reset)
0x1 : B_0x1
HSE ready interrupt
enabled
End of enumeration elements list.
CSIRDYIE : CSIRDYIE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CSI ready interrupt disabled
(default after reset)
0x1 : B_0x1
CSI ready interrupt
enabled
End of enumeration elements list.
PLL1DYIE : PLL1DYIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL1 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL1 lock interrupt
enabled
End of enumeration elements list.
PLL2DYIE : PLL2DYIE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL2 lock interrupt
enabled
End of enumeration elements list.
PLL3DYIE : PLL3DYIE
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL3 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL3 lock interrupt
enabled
End of enumeration elements list.
PLL4DYIE : PLL4DYIE
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL4 lock interrupt disabled
(default after reset)
0x1 : B_0x1
PLL4 lock interrupt
enabled
End of enumeration elements list.
LSECSSIE : LSECSSIE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE CSS interrupt disabled (default
after reset)
0x1 : B_0x1
LSE CSS interrupt
enabled
End of enumeration elements list.
WKUPIE : WKUPIE
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wake-up interrupt disabled (default
after reset)
0x1 : B_0x1
Wake-up interrupt
enabled
End of enumeration elements list.
This register shall be used by the MCU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Please refer to Section1.5: RCC Interrupts for more details.
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSIRDYF
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the LSI (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
LSI, writing clears this flag
End of enumeration elements list.
LSERDYF : LSERDYF
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the LSE (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
LSE, writing clears this flag
End of enumeration elements list.
HSIRDYF : HSIRDYF
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the HSI (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
HSI, writing clears this flag
End of enumeration elements list.
HSERDYF : HSERDYF
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the HSE (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
HSE, writing clears this flag
End of enumeration elements list.
CSIRDYF : CSIRDYF
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
the CSI (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by the
CSI, writing clears this flag
End of enumeration elements list.
PLL1DYF : PLL1DYF
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL1 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL1
lock, writing clears this flag
End of enumeration elements list.
PLL2DYF : PLL2DYF
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL2 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL2
lock, writing clears this flag
End of enumeration elements list.
PLL3DYF : PLL3DYF
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL3 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL3
lock, writing clears this flag
End of enumeration elements list.
PLL4DYF : PLL4DYF
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by
PLL4 lock (default after reset)
0x1 : B_0x1
Clock ready interrupt caused by PLL4
lock, writing clears this flag
End of enumeration elements list.
LSECSSF : LSECSSF
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No failure detected on the external
32 kHz oscillator (default after
reset)
0x1 : B_0x1
A failure is detected on the
external 32 kHz oscillator, writing clears this
flag
End of enumeration elements list.
WKUPF : WKUPF
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No wake-up interrupt pending
(default after reset)
0x1 : B_0x1
Wake-up interrupt pending, writing
clears this flag
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6SRC : SPI6SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk5 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
hse_ker_ck clock selected as kernel
peripheral clock
0x5 : B_0x5
pll3_q_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART1SRC : UART1SRC
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pclk5 clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll3_q_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
hsi_ker_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
csi_ker_ck clock selected as kernel
peripheral clock
0x4 : B_0x4
pll4_q_ck clock selected as kernel
peripheral clock
0x5 : B_0x5
hse_ker_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNG1SRC : RNG1SRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
csi_ker_ck clock selected as kernel
peripheral clock (default after
reset)
0x1 : B_0x1
pll4_r_ck clock selected as kernel
peripheral clock
0x2 : B_0x2
lse_ck clock selected as kernel
peripheral clock
0x3 : B_0x3
lsi_ck clock selected as kernel
peripheral clock
End of enumeration elements list.
This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Please refer to Section1.4.10.1: Clock Enabling Delays.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKPERSRC : CKPERSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hsi_ker_ck clock selected (default
after reset)
0x1 : B_0x1
csi_ker_ck clock
selected
0x2 : B_0x2
hse_ker_ck clock
selected
0x3 : B_0x3
Clock disabled
End of enumeration elements list.
This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STGENSRC : STGENSRC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
hsi_ker_ck clock selected (default
after reset)
0x1 : B_0x1
hse_ker_ck clock
selected
End of enumeration elements list.
This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDRC1EN : DDRC1EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Means that the DDRC peripheral
clocks are disabled
0x1 : B_0x1
Means that the DDRC peripheral
clocks are enabled
End of enumeration elements list.
DDRC1LPEN : DDRC1LPEN
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the peripheral clocks are
disabled in CSLEEP
0x1 : B_0x1
means that the peripheral clocks are
enabled in CSLEEP
End of enumeration elements list.
DDRC2EN : DDRC2EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Means that the DDRC peripheral
clocks are disabled
0x1 : B_0x1
Means that the DDRC peripheral
clocks are enabled
End of enumeration elements list.
DDRC2LPEN : DDRC2LPEN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the peripheral clocks are
disabled in CSLEEP
0x1 : B_0x1
means that the peripheral clocks are
enabled in CSLEEP
End of enumeration elements list.
DDRPHYCEN : DDRPHYCEN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the peripheral clocks are
disabled
0x1 : B_0x1
means that the peripheral clocks are
enabled
End of enumeration elements list.
DDRPHYCLPEN : DDRPHYCLPEN
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the peripheral clocks are
disabled in CSLEEP
0x1 : B_0x1
means that the peripheral clocks are
enabled in CSLEEP
End of enumeration elements list.
DDRCAPBEN : DDRCAPBEN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the APB clock is
disabled
0x1 : B_0x1
means that the APB clock is
enabled
End of enumeration elements list.
DDRCAPBLPEN : DDRCAPBLPEN
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the APB clock is disabled
in CSLEEP
0x1 : B_0x1
means that the APB clock is enabled
in CSLEEP
End of enumeration elements list.
AXIDCGEN : AXIDCGEN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the dynamic clock gating
of AXIDCG[2:1] is disabled during MPU
CRUN,
0x1 : B_0x1
means that the dynamic clock gating
of AXIDCG{2:1] is enabled during MPU
CRUN
End of enumeration elements list.
DDRPHYCAPBEN : DDRPHYCAPBEN
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the APB clock is
disabled
0x1 : B_0x1
means that the APB clock is
enabled
End of enumeration elements list.
DDRPHYCAPBLPEN : DDRPHYCAPBLPEN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
means that the APB clock is disabled
in CSLEEP
0x1 : B_0x1
means that the APB clock is enabled
in CSLEEP
End of enumeration elements list.
KERDCG_DLY : KERDCG_DLY
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 period of ddrc_ker_ck between
cactive_ddrc falling edge and the gating of
ddrc_ker_ckg.
0x1 : B_0x1
3 periods of ddrc_ker_ck between
cactive_ddrc falling edge and the gating of
ddrc_ker_ckg.
0x7 : B_0x7
15 periods of ddrc_ker_ck between
cactive_ddrc falling edge and the gating of
ddrc_ker_ckg.
End of enumeration elements list.
DDRCAPBRST : DDRCAPBRST
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
does not reset the DDRC APB
interface
0x1 : B_0x1
resets the DDRC APB
interface
End of enumeration elements list.
DDRCAXIRST : DDRCAXIRST
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
does not reset the DDRC AXI
interface
0x1 : B_0x1
resets the DDRC AXI
interface
End of enumeration elements list.
DDRCORERST : DDRCORERST
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
does not reset the DDRC
core
0x1 : B_0x1
resets the DDRC core
End of enumeration elements list.
DPHYAPBRST : DPHYAPBRST
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
does not reset the DDRPHYC APB
interface
0x1 : B_0x1
resets the DDRPHYC APB
interface
End of enumeration elements list.
DPHYRST : DPHYRST
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
does not reset the
DDRPHYC
0x1 : B_0x1
resets the DDRPHYC
End of enumeration elements list.
DPHYCTLRST : DPHYCTLRST
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
does not reset the DDRPHYC
Control
0x1 : B_0x1
resets the DDRPHYC
Control
End of enumeration elements list.
DDRCKMOD : DDRCKMOD
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Normal mode: the gating of the
dphy_ker_ck clock depends on the DDRPHYCEN,
DDRPHYCLPEN and MPU mode. The gating of the
ddrc_ker_ckg clock depends on the DDRCxEN,
DDRCxLPEN and MPU mode. This mode must be
selected during DDRC and DDRPHYC initialization
phase, and if the application is using the
software self-refresh (SSR).
0x1 : B_0x1
Automatic Self-Refresh mode (ASR1):
the clock ddrc_ker_ckg is gated automatically
according to cactive_ddrc signal. The gating of
the dphy_ker_ck clock depends on the DDRPHYCEN,
DDRPHYCLPEN and MPU mode.
0x2 : B_0x2
Hardware Self-Refresh mode (HSR1):
the gating of the ddrc_ker_ckg clock is
controlled by the AXI-Low-Power interface
connected to the DDRC. The gating of the
dphy_ker_ck clock depends on the DDRPHYCEN,
DDRPHYCLPEN and MPU mode.
0x5 : B_0x5
Full Automatic Self-Refresh mode
(ASR2): the clocks ddrc_ker_ckg and dphy_ker_ck
are gated automatically according to cactive_ddrc
signal.
0x6 : B_0x6
Full Hardware Self-Refresh mode
(HSR2): the gating of ddrc_ker_ckg and
dphy_ker_ck clocks are controlled by the
AXI-Low-Power interface connected to the
DDRC.
End of enumeration elements list.
GSKPMOD : GSKPMOD
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The GSKP block is controlled by the
GSKPCTRL bit.
0x1 : B_0x1
The GSKP block is controlled
automatically by the DFI.
End of enumeration elements list.
GSKPCTRL : GSKPCTRL
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The GSKP block is providing the
clock phy_out_ck (provided by the
DDRPHYC)
0x1 : B_0x1
The GSKP block is providing the
clock dphy_ker_ck (provided by the
RCC)
End of enumeration elements list.
DFILP_WIDTH : DFILP_WIDTH
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bypass, delay disabled
0x1 : B_0x1
Forces a delay of 160 x Tdphy_ker_ck
to be used when Fdphy_ker_ck is between 120 and
160 MHz.
0x2 : B_0x2
Forces a delay of 224 x Tdphy_ker_ck
to be used when Fdphy_ker_ck is between 160 and
220 MHz.
0x3 : B_0x3
Forces a delay of 320 x Tdphy_ker_ck
to be used when Fdphy_ker_ck is between 220 and
320 MHz.
0x4 : B_0x4
Forces a delay of 416 x Tdphy_ker_ck
to be used when Fdphy_ker_ck is between 320 and
410 MHz.
End of enumeration elements list.
GSKP_DUR : GSKP_DUR
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sets a delay of 32 x
Tdphy_ker_ck
0x1 : B_0x1
Sets a delay of 2 x 32 x
Tdphy_ker_ck
0x2 : B_0x2
Sets a delay of 3 x 32 x
Tdphy_ker_ck
0xF : B_0xF
Sets a delay of 16 x 32 x
Tdphy_ker_ck
End of enumeration elements list.
This register gives the IP version
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only
This register gives the unique identifier of the RCC
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
This register gives the decoding space, which is for the RCC of 4 kB.
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
access : read-only
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