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GICD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GICD_CTLR (CTLR)

GICD_CTLRNS (CTLRNS)

ISENABLER0

ISENABLER1

ISENABLER2

ISENABLER3

ISENABLER4

ISENABLER5

ISENABLER6

ISENABLER7

ISENABLER8

ISACTIVER0

ICENABLER0

ICENABLER1

ICENABLER2

ICENABLER3

ICENABLER4

ICENABLER5

ICENABLER6

ICENABLER7

ICENABLER8

ISPENDR0

ISPENDR1

ISPENDR2

ISPENDR3

ISPENDR4

ISPENDR5

ISPENDR6

ISPENDR7

ISPENDR8

ICPENDR0

ICPENDR1

ICPENDR2

ICPENDR3

ICPENDR4

ICPENDR5

ICPENDR6

ICPENDR7

ICPENDR8

ISACTIVER1

ISACTIVER2

ISACTIVER3

ISACTIVER4

ISACTIVER5

ISACTIVER6

ISACTIVER7

ISACTIVER8

ICACTIVER0

ICACTIVER1

ICACTIVER2

ICACTIVER3

ICACTIVER4

ICACTIVER5

ICACTIVER6

ICACTIVER7

ICACTIVER8

GICD_TYPER (TYPER)

IPRIORITYR0

IPRIORITYR1

IPRIORITYR2

IPRIORITYR3

IPRIORITYR4

IPRIORITYR5

IPRIORITYR6

IPRIORITYR7

IPRIORITYR8

IPRIORITYR9

IPRIORITYR10

IPRIORITYR11

IPRIORITYR12

IPRIORITYR13

IPRIORITYR14

IPRIORITYR15

IPRIORITYR16

IPRIORITYR17

IPRIORITYR18

IPRIORITYR19

IPRIORITYR20

IPRIORITYR21

IPRIORITYR22

IPRIORITYR23

IPRIORITYR24

IPRIORITYR25

IPRIORITYR26

IPRIORITYR27

IPRIORITYR28

IPRIORITYR29

IPRIORITYR30

IPRIORITYR31

IPRIORITYR32

IPRIORITYR33

IPRIORITYR34

IPRIORITYR35

IPRIORITYR36

IPRIORITYR37

IPRIORITYR38

IPRIORITYR39

IPRIORITYR40

IPRIORITYR41

IPRIORITYR42

IPRIORITYR43

IPRIORITYR44

IPRIORITYR45

IPRIORITYR46

IPRIORITYR47

IPRIORITYR48

IPRIORITYR49

IPRIORITYR50

IPRIORITYR51

IPRIORITYR52

IPRIORITYR53

IPRIORITYR54

IPRIORITYR55

IPRIORITYR56

IPRIORITYR57

IPRIORITYR58

IPRIORITYR59

IPRIORITYR60

IPRIORITYR61

IPRIORITYR62

IPRIORITYR63

IPRIORITYR64

IPRIORITYR65

IPRIORITYR66

IPRIORITYR67

IPRIORITYR68

IPRIORITYR69

IPRIORITYR70

IPRIORITYR71

GICD_IIDR (IIDR)

GICD_IGROUPR0 (IGROUPR0)

ITARGETSR0

ITARGETSR1

ITARGETSR2

ITARGETSR3

ITARGETSR4

ITARGETSR5

ITARGETSR6

ITARGETSR7

ITARGETSR8

ITARGETSR9

ITARGETSR10

ITARGETSR11

ITARGETSR12

ITARGETSR13

ITARGETSR14

ITARGETSR15

GICD_IGROUPR1 (IGROUPR1)

ITARGETSR16

ITARGETSR17

ITARGETSR18

ITARGETSR19

ITARGETSR20

ITARGETSR21

ITARGETSR22

ITARGETSR23

ITARGETSR24

ITARGETSR25

ITARGETSR26

ITARGETSR27

ITARGETSR28

ITARGETSR29

ITARGETSR30

ITARGETSR31

GICD_IGROUPR2 (IGROUPR2)

ITARGETSR32

ITARGETSR33

ITARGETSR34

ITARGETSR35

ITARGETSR36

ITARGETSR37

ITARGETSR38

ITARGETSR39

ITARGETSR40

ITARGETSR41

ITARGETSR42

ITARGETSR43

ITARGETSR44

ITARGETSR45

ITARGETSR46

ITARGETSR47

GICD_IGROUPR3 (IGROUPR3)

ITARGETSR48

ITARGETSR49

ITARGETSR50

ITARGETSR51

ITARGETSR52

ITARGETSR53

ITARGETSR54

ITARGETSR55

ITARGETSR56

ITARGETSR57

ITARGETSR58

ITARGETSR59

ITARGETSR60

ITARGETSR61

ITARGETSR62

ITARGETSR63

GICD_IGROUPR4 (IGROUPR4)

ITARGETSR64

ITARGETSR65

ITARGETSR66

ITARGETSR67

ITARGETSR68

ITARGETSR69

ITARGETSR70

ITARGETSR71

GICD_IGROUPR5 (IGROUPR5)

GICD_IGROUPR6 (IGROUPR6)

GICD_IGROUPR7 (IGROUPR7)

GICD_IGROUPR8 (IGROUPR8)

ICFGR0

ICFGR1

ICFGR2

ICFGR3

ICFGR4

ICFGR5

ICFGR6

ICFGR7

ICFGR8

ICFGR9

ICFGR10

ICFGR11

ICFGR12

ICFGR13

ICFGR14

ICFGR15

ICFGR16

ICFGR17

PPISR

SPISR0

SPISR1

SPISR2

SPISR3

SPISR4

SPISR5

SPISR6

SPISR7

SGIR

CPENDSGIR0

CPENDSGIR1

CPENDSGIR2

CPENDSGIR3

SPENDSGIR0

SPENDSGIR1

SPENDSGIR2

SPENDSGIR3

PIDR4

PIDR5

PIDR6

PIDR7

PIDR0

PIDR1

PIDR2

PIDR3

CIDR0

CIDR1

CIDR2

CIDR3


GICD_CTLR (CTLR)

GICD control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_CTLR GICD_CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLEGRP0 ENABLEGRP1

ENABLEGRP0 : enable group 0 interrupts
bits : 0 - 0 (1 bit)
access : read-write

ENABLEGRP1 : enable group 1 interrupts
bits : 1 - 1 (1 bit)


GICD_CTLRNS (CTLRNS)

GICD control (non-secure access) register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GICD_CTLR
reset_Mask : 0x0

GICD_CTLRNS GICD_CTLRNS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces
bits : 0 - 0 (1 bit)


ISENABLER0

GICD interrupt set-enable register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER0 ISENABLER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER0

ISENABLER0 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER1

GICD interrupt set-enable register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER1 ISENABLER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER1

ISENABLER1 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER2

GICD interrupt set-enable register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER2 ISENABLER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER2

ISENABLER2 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER3

GICD interrupt set-enable register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER3 ISENABLER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER3

ISENABLER3 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER4

GICD interrupt set-enable register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER4 ISENABLER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER4

ISENABLER4 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER5

GICD interrupt set-enable register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER5 ISENABLER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER5

ISENABLER5 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER6

GICD interrupt set-enable register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER6 ISENABLER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER6

ISENABLER6 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER7

GICD interrupt set-enable register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER7 ISENABLER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER7

ISENABLER7 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISENABLER8

GICD interrupt set-enable register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISENABLER8 ISENABLER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISENABLER8

ISENABLER8 : interrupt set-enable
bits : 0 - 31 (32 bit)


ISACTIVER0

GICD interrupt set-active registers
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER0 ISACTIVER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER0

ISACTIVER0 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICENABLER0

GICD interrupt clear-enable register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER0 ICENABLER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER0

ICENABLER0 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER1

GICD interrupt clear-enable register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER1 ICENABLER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER1

ICENABLER1 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER2

GICD interrupt clear-enable register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER2 ICENABLER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER2

ICENABLER2 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER3

GICD interrupt clear-enable register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER3 ICENABLER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER3

ICENABLER3 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER4

GICD interrupt clear-enable register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER4 ICENABLER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER4

ICENABLER4 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER5

GICD interrupt clear-enable register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER5 ICENABLER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER5

ICENABLER5 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER6

GICD interrupt clear-enable register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER6 ICENABLER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER6

ICENABLER6 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER7

GICD interrupt clear-enable register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER7 ICENABLER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER7

ICENABLER7 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ICENABLER8

GICD interrupt clear-enable register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICENABLER8 ICENABLER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICENABLER8

ICENABLER8 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)


ISPENDR0

GICD interrupt set-pending registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR0 ISPENDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR0

ISPENDR0 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR1

GICD interrupt set-pending registers
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR1 ISPENDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR1

ISPENDR1 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR2

GICD interrupt set-pending registers
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR2 ISPENDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR2

ISPENDR2 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR3

GICD interrupt set-pending registers
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR3 ISPENDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR3

ISPENDR3 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR4

GICD interrupt set-pending registers
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR4 ISPENDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR4

ISPENDR4 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR5

GICD interrupt set-pending registers
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR5 ISPENDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR5

ISPENDR5 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR6

GICD interrupt set-pending registers
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR6 ISPENDR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR6

ISPENDR6 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR7

GICD interrupt set-pending registers
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR7 ISPENDR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR7

ISPENDR7 : interrupt set-pending
bits : 0 - 31 (32 bit)


ISPENDR8

GICD interrupt set-pending registers
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPENDR8 ISPENDR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPENDR8

ISPENDR8 : interrupt set-pending
bits : 0 - 31 (32 bit)


ICPENDR0

GICD interrupt clear-pending registers
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR0 ICPENDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR0

ICPENDR0 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR1

GICD interrupt clear-pending registers
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR1 ICPENDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR1

ICPENDR1 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR2

GICD interrupt clear-pending registers
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR2 ICPENDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR2

ICPENDR2 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR3

GICD interrupt clear-pending registers
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR3 ICPENDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR3

ICPENDR3 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR4

GICD interrupt clear-pending registers
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR4 ICPENDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR4

ICPENDR4 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR5

GICD interrupt clear-pending registers
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR5 ICPENDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR5

ICPENDR5 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR6

GICD interrupt clear-pending registers
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR6 ICPENDR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR6

ICPENDR6 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR7

GICD interrupt clear-pending registers
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR7 ICPENDR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR7

ICPENDR7 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICPENDR8

GICD interrupt clear-pending registers
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPENDR8 ICPENDR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICPENDR8

ICPENDR8 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER1

GICD interrupt set-active registers
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER1 ISACTIVER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER1

ISACTIVER1 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER2

GICD interrupt set-active registers
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER2 ISACTIVER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER2

ISACTIVER2 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER3

GICD interrupt set-active registers
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER3 ISACTIVER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER3

ISACTIVER3 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER4

GICD interrupt set-active registers
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER4 ISACTIVER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER4

ISACTIVER4 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER5

GICD interrupt set-active registers
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER5 ISACTIVER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER5

ISACTIVER5 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER6

GICD interrupt set-active registers
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER6 ISACTIVER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER6

ISACTIVER6 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER7

GICD interrupt set-active registers
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER7 ISACTIVER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER7

ISACTIVER7 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ISACTIVER8

GICD interrupt set-active registers
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISACTIVER8 ISACTIVER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISACTIVER8

ISACTIVER8 : interrupt clear-pending
bits : 0 - 31 (32 bit)


ICACTIVER0

GICD interrupt clear-active registers
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER0 ICACTIVER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER0

ICACTIVER0 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER1

GICD interrupt clear-active registers
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER1 ICACTIVER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER1

ICACTIVER1 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER2

GICD interrupt clear-active registers
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER2 ICACTIVER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER2

ICACTIVER2 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER3

GICD interrupt clear-active registers
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER3 ICACTIVER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER3

ICACTIVER3 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER4

GICD interrupt clear-active registers
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER4 ICACTIVER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER4

ICACTIVER4 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER5

GICD interrupt clear-active registers
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER5 ICACTIVER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER5

ICACTIVER5 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER6

GICD interrupt clear-active registers
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER6 ICACTIVER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER6

ICACTIVER6 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER7

GICD interrupt clear-active registers
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER7 ICACTIVER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER7

ICACTIVER7 : interrupt clear-active
bits : 0 - 31 (32 bit)


ICACTIVER8

GICD interrupt clear-active registers
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACTIVER8 ICACTIVER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICACTIVER8

ICACTIVER8 : interrupt clear-active
bits : 0 - 31 (32 bit)


GICD_TYPER (TYPER)

GICD interrupt controller type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICD_TYPER GICD_TYPER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITLINESNUMBER CPUNUMBER SECURITYEXTN LSPI

ITLINESNUMBER : number of interrupt lines
bits : 0 - 4 (5 bit)

CPUNUMBER : number of processors interfaces
bits : 5 - 7 (3 bit)

SECURITYEXTN : security extension
bits : 10 - 10 (1 bit)

LSPI : lockable shared peripheral interrupt
bits : 11 - 15 (5 bit)


IPRIORITYR0

GICD interrupt priority registers
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR0 IPRIORITYR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR1

GICD interrupt priority registers
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR1 IPRIORITYR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR2

GICD interrupt priority registers
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR2 IPRIORITYR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR3

GICD interrupt priority registers
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR3 IPRIORITYR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR4

GICD interrupt priority registers
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR4 IPRIORITYR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR5

GICD interrupt priority registers
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR5 IPRIORITYR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR6

GICD interrupt priority registers
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR6 IPRIORITYR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR7

GICD interrupt priority registers
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR7 IPRIORITYR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR8

GICD interrupt priority registers
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR8 IPRIORITYR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR9

GICD interrupt priority registers
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR9 IPRIORITYR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR10

GICD interrupt priority registers
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR10 IPRIORITYR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR11

GICD interrupt priority registers
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR11 IPRIORITYR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR12

GICD interrupt priority registers
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR12 IPRIORITYR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR13

GICD interrupt priority registers
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR13 IPRIORITYR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR14

GICD interrupt priority registers
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR14 IPRIORITYR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR15

GICD interrupt priority registers
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR15 IPRIORITYR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR16

GICD interrupt priority registers
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR16 IPRIORITYR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR17

GICD interrupt priority registers
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR17 IPRIORITYR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR18

GICD interrupt priority registers
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR18 IPRIORITYR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR19

GICD interrupt priority registers
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR19 IPRIORITYR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR20

GICD interrupt priority registers
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR20 IPRIORITYR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR21

GICD interrupt priority registers
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR21 IPRIORITYR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR22

GICD interrupt priority registers
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR22 IPRIORITYR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR23

GICD interrupt priority registers
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR23 IPRIORITYR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR24

GICD interrupt priority registers
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR24 IPRIORITYR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR25

GICD interrupt priority registers
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR25 IPRIORITYR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR26

GICD interrupt priority registers
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR26 IPRIORITYR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR27

GICD interrupt priority registers
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR27 IPRIORITYR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR28

GICD interrupt priority registers
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR28 IPRIORITYR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR29

GICD interrupt priority registers
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR29 IPRIORITYR29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR30

GICD interrupt priority registers
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR30 IPRIORITYR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR31

GICD interrupt priority registers
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR31 IPRIORITYR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR32

GICD interrupt priority registers
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR32 IPRIORITYR32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR33

GICD interrupt priority registers
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR33 IPRIORITYR33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR34

GICD interrupt priority registers
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR34 IPRIORITYR34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR35

GICD interrupt priority registers
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR35 IPRIORITYR35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR36

GICD interrupt priority registers
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR36 IPRIORITYR36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR37

GICD interrupt priority registers
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR37 IPRIORITYR37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR38

GICD interrupt priority registers
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR38 IPRIORITYR38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR39

GICD interrupt priority registers
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR39 IPRIORITYR39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR40

GICD interrupt priority registers
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR40 IPRIORITYR40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR41

GICD interrupt priority registers
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR41 IPRIORITYR41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR42

GICD interrupt priority registers
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR42 IPRIORITYR42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR43

GICD interrupt priority registers
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR43 IPRIORITYR43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR44

GICD interrupt priority registers
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR44 IPRIORITYR44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR45

GICD interrupt priority registers
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR45 IPRIORITYR45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR46

GICD interrupt priority registers
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR46 IPRIORITYR46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR47

GICD interrupt priority registers
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR47 IPRIORITYR47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR48

GICD interrupt priority registers
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR48 IPRIORITYR48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR49

GICD interrupt priority registers
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR49 IPRIORITYR49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR50

GICD interrupt priority registers
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR50 IPRIORITYR50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR51

GICD interrupt priority registers
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR51 IPRIORITYR51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR52

GICD interrupt priority registers
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR52 IPRIORITYR52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR53

GICD interrupt priority registers
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR53 IPRIORITYR53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR54

GICD interrupt priority registers
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR54 IPRIORITYR54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR55

GICD interrupt priority registers
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR55 IPRIORITYR55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR56

GICD interrupt priority registers
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR56 IPRIORITYR56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR57

GICD interrupt priority registers
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR57 IPRIORITYR57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR58

GICD interrupt priority registers
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR58 IPRIORITYR58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR59

GICD interrupt priority registers
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR59 IPRIORITYR59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR60

GICD interrupt priority registers
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR60 IPRIORITYR60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR61

GICD interrupt priority registers
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR61 IPRIORITYR61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR62

GICD interrupt priority registers
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR62 IPRIORITYR62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR63

GICD interrupt priority registers
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR63 IPRIORITYR63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR64

GICD interrupt priority registers
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR64 IPRIORITYR64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR65

GICD interrupt priority registers
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR65 IPRIORITYR65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR66

GICD interrupt priority registers
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR66 IPRIORITYR66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR67

GICD interrupt priority registers
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR67 IPRIORITYR67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR68

GICD interrupt priority registers
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR68 IPRIORITYR68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR69

GICD interrupt priority registers
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR69 IPRIORITYR69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR70

GICD interrupt priority registers
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR70 IPRIORITYR70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


IPRIORITYR71

GICD interrupt priority registers
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIORITYR71 IPRIORITYR71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3

PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)

PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)

PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)

PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)


GICD_IIDR (IIDR)

GICD implementer identification register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICD_IIDR GICD_IIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMPLEMENTER VARIANT REVISION PRODUCTID

IMPLEMENTER : GIC implementer
bits : 0 - 11 (12 bit)

VARIANT : major revision number of the GIC
bits : 12 - 15 (4 bit)

REVISION : minor revision number of the GIC
bits : 16 - 19 (4 bit)

PRODUCTID : product ID of the GIC
bits : 24 - 31 (8 bit)


GICD_IGROUPR0 (IGROUPR0)

GICD interrupt group registers
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR0 GICD_IGROUPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR0

IGROUPR0 : group of interrupts
bits : 0 - 31 (32 bit)


ITARGETSR0

GICD interrupt processor target registers
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR0 ITARGETSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR1

GICD interrupt processor target registers
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR1 ITARGETSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR2

GICD interrupt processor target registers
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR2 ITARGETSR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR3

GICD interrupt processor target registers
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR3 ITARGETSR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR4

GICD interrupt processor target registers
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR4 ITARGETSR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR5

GICD interrupt processor target registers
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR5 ITARGETSR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR6

GICD interrupt processor target registers
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR6 ITARGETSR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR7

GICD interrupt processor target registers
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR7 ITARGETSR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR8

GICD interrupt processor target registers
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR8 ITARGETSR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR9

GICD interrupt processor target registers
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR9 ITARGETSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR10

GICD interrupt processor target registers
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR10 ITARGETSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR11

GICD interrupt processor target registers
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR11 ITARGETSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR12

GICD interrupt processor target registers
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR12 ITARGETSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR13

GICD interrupt processor target registers
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR13 ITARGETSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR14

GICD interrupt processor target registers
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR14 ITARGETSR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR15

GICD interrupt processor target registers
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR15 ITARGETSR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


GICD_IGROUPR1 (IGROUPR1)

GICD interrupt group registers
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR1 GICD_IGROUPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR1

IGROUPR1 : group of interrupts
bits : 0 - 31 (32 bit)


ITARGETSR16

GICD interrupt processor target registers
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR16 ITARGETSR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR17

GICD interrupt processor target registers
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR17 ITARGETSR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR18

GICD interrupt processor target registers
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR18 ITARGETSR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR19

GICD interrupt processor target registers
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR19 ITARGETSR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR20

GICD interrupt processor target registers
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR20 ITARGETSR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR21

GICD interrupt processor target registers
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR21 ITARGETSR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR22

GICD interrupt processor target registers
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR22 ITARGETSR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR23

GICD interrupt processor target registers
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR23 ITARGETSR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR24

GICD interrupt processor target registers
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR24 ITARGETSR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR25

GICD interrupt processor target registers
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR25 ITARGETSR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR26

GICD interrupt processor target registers
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR26 ITARGETSR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR27

GICD interrupt processor target registers
address_offset : 0x86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR27 ITARGETSR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR28

GICD interrupt processor target registers
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR28 ITARGETSR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR29

GICD interrupt processor target registers
address_offset : 0x874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR29 ITARGETSR29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR30

GICD interrupt processor target registers
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR30 ITARGETSR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR31

GICD interrupt processor target registers
address_offset : 0x87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR31 ITARGETSR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


GICD_IGROUPR2 (IGROUPR2)

GICD interrupt group registers
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR2 GICD_IGROUPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR2

IGROUPR2 : group of interrupts
bits : 0 - 31 (32 bit)


ITARGETSR32

GICD interrupt processor target registers
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR32 ITARGETSR32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR33

GICD interrupt processor target registers
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR33 ITARGETSR33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR34

GICD interrupt processor target registers
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR34 ITARGETSR34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR35

GICD interrupt processor target registers
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR35 ITARGETSR35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR36

GICD interrupt processor target registers
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR36 ITARGETSR36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR37

GICD interrupt processor target registers
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR37 ITARGETSR37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR38

GICD interrupt processor target registers
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR38 ITARGETSR38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR39

GICD interrupt processor target registers
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR39 ITARGETSR39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR40

GICD interrupt processor target registers
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR40 ITARGETSR40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR41

GICD interrupt processor target registers
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR41 ITARGETSR41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR42

GICD interrupt processor target registers
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR42 ITARGETSR42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR43

GICD interrupt processor target registers
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR43 ITARGETSR43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR44

GICD interrupt processor target registers
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR44 ITARGETSR44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR45

GICD interrupt processor target registers
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR45 ITARGETSR45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR46

GICD interrupt processor target registers
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR46 ITARGETSR46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR47

GICD interrupt processor target registers
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR47 ITARGETSR47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


GICD_IGROUPR3 (IGROUPR3)

GICD interrupt group registers
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR3 GICD_IGROUPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR3

IGROUPR3 : group of interrupts
bits : 0 - 31 (32 bit)


ITARGETSR48

GICD interrupt processor target registers
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR48 ITARGETSR48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR49

GICD interrupt processor target registers
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR49 ITARGETSR49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR50

GICD interrupt processor target registers
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR50 ITARGETSR50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR51

GICD interrupt processor target registers
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR51 ITARGETSR51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR52

GICD interrupt processor target registers
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR52 ITARGETSR52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR53

GICD interrupt processor target registers
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR53 ITARGETSR53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR54

GICD interrupt processor target registers
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR54 ITARGETSR54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR55

GICD interrupt processor target registers
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR55 ITARGETSR55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR56

GICD interrupt processor target registers
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR56 ITARGETSR56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR57

GICD interrupt processor target registers
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR57 ITARGETSR57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR58

GICD interrupt processor target registers
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR58 ITARGETSR58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR59

GICD interrupt processor target registers
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR59 ITARGETSR59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR60

GICD interrupt processor target registers
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR60 ITARGETSR60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR61

GICD interrupt processor target registers
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR61 ITARGETSR61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR62

GICD interrupt processor target registers
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR62 ITARGETSR62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR63

GICD interrupt processor target registers
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR63 ITARGETSR63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


GICD_IGROUPR4 (IGROUPR4)

GICD interrupt group registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR4 GICD_IGROUPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR4

IGROUPR4 : group of interrupts
bits : 0 - 31 (32 bit)


ITARGETSR64

GICD interrupt processor target registers
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR64 ITARGETSR64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR65

GICD interrupt processor target registers
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR65 ITARGETSR65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR66

GICD interrupt processor target registers
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR66 ITARGETSR66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR67

GICD interrupt processor target registers
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR67 ITARGETSR67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR68

GICD interrupt processor target registers
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR68 ITARGETSR68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR69

GICD interrupt processor target registers
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR69 ITARGETSR69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR70

GICD interrupt processor target registers
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR70 ITARGETSR70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


ITARGETSR71

GICD interrupt processor target registers
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITARGETSR71 ITARGETSR71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU_TARGETS0 CPU_TARGETS1 CPU_TARGETS2 CPU_TARGETS3

CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)

CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)

CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)

CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)


GICD_IGROUPR5 (IGROUPR5)

GICD interrupt group registers
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR5 GICD_IGROUPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR5

IGROUPR5 : group of interrupts
bits : 0 - 31 (32 bit)


GICD_IGROUPR6 (IGROUPR6)

GICD interrupt group registers
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR6 GICD_IGROUPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR6

IGROUPR6 : group of interrupts
bits : 0 - 31 (32 bit)


GICD_IGROUPR7 (IGROUPR7)

GICD interrupt group registers
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR7 GICD_IGROUPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR7

IGROUPR7 : group of interrupts
bits : 0 - 31 (32 bit)


GICD_IGROUPR8 (IGROUPR8)

GICD interrupt group registers
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICD_IGROUPR8 GICD_IGROUPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGROUPR8

IGROUPR8 : group of interrupts
bits : 0 - 31 (32 bit)


ICFGR0

GICD interrupt configuration register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR0 ICFGR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR1

GICD interrupt configuration register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR1 ICFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR2

GICD interrupt configuration register
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR2 ICFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR3

GICD interrupt configuration register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR3 ICFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR4

GICD interrupt configuration register
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR4 ICFGR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR5

GICD interrupt configuration register
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR5 ICFGR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR6

GICD interrupt configuration register
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR6 ICFGR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR7

GICD interrupt configuration register
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR7 ICFGR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR8

GICD interrupt configuration register
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR8 ICFGR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR9

GICD interrupt configuration register
address_offset : 0xC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR9 ICFGR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR10

GICD interrupt configuration register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR10 ICFGR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR11

GICD interrupt configuration register
address_offset : 0xC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR11 ICFGR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR12

GICD interrupt configuration register
address_offset : 0xC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR12 ICFGR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR13

GICD interrupt configuration register
address_offset : 0xC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR13 ICFGR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR14

GICD interrupt configuration register
address_offset : 0xC38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR14 ICFGR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR15

GICD interrupt configuration register
address_offset : 0xC3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR15 ICFGR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR16

GICD interrupt configuration register
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR16 ICFGR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


ICFGR17

GICD interrupt configuration register
address_offset : 0xC44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICFGR17 ICFGR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_CONFIG0 INT_CONFIG1 INT_CONFIG2 INT_CONFIG3 INT_CONFIG4 INT_CONFIG5 INT_CONFIG6 INT_CONFIG7 INT_CONFIG8 INT_CONFIG9 INT_CONFIG10 INT_CONFIG11 INT_CONFIG12 INT_CONFIG13 INT_CONFIG14 INT_CONFIG15

INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)

INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)

INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)

INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)

INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)

INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)

INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)

INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)

INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)

INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)

INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)

INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)

INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)

INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)

INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)

INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)


PPISR

GICD private peripheral interrupt status register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PPISR PPISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPI6 PPI5 PPI4 PPI0 PPI1 PPI2 PPI3

PPI6 : virtual maintenance interrupt
bits : 9 - 9 (1 bit)

PPI5 : hypervisor timer event
bits : 10 - 10 (1 bit)

PPI4 : virtual timer event
bits : 11 - 11 (1 bit)

PPI0 : nFIQ (not used)
bits : 12 - 12 (1 bit)

PPI1 : secure physical timer event
bits : 13 - 13 (1 bit)

PPI2 : secure physical timer event
bits : 14 - 14 (1 bit)

PPI3 : nIRQ (not used)
bits : 15 - 15 (1 bit)


SPISR0

GICD shared peripheral interrupt registers
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR0 SPISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR0

SPISR0 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR1

GICD shared peripheral interrupt registers
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR1 SPISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR1

SPISR1 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR2

GICD shared peripheral interrupt registers
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR2 SPISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR2

SPISR2 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR3

GICD shared peripheral interrupt registers
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR3 SPISR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR3

SPISR3 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR4

GICD shared peripheral interrupt registers
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR4 SPISR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR4

SPISR4 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR5

GICD shared peripheral interrupt registers
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR5 SPISR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR5

SPISR5 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR6

GICD shared peripheral interrupt registers
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR6 SPISR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR6

SPISR6 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SPISR7

GICD shared peripheral interrupt registers
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPISR7 SPISR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPISR7

SPISR7 : shared peripheral interrupt
bits : 0 - 31 (32 bit)


SGIR

GICD software generated interrupt register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SGIR SGIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGIINTID NSATT CPUTARGETLIST TARGETLISTFILTER

SGIINTID : SGI interrupt ID
bits : 0 - 3 (4 bit)

NSATT : non-secure attribute
bits : 15 - 15 (1 bit)

CPUTARGETLIST : CPU target list
bits : 16 - 17 (2 bit)

TARGETLISTFILTER : target list filter
bits : 24 - 25 (2 bit)


CPENDSGIR0

GICD SGI clear-pending registers
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPENDSGIR0 CPENDSGIR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING3

SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


CPENDSGIR1

GICD SGI clear-pending registers
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPENDSGIR1 CPENDSGIR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING3

SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


CPENDSGIR2

GICD SGI clear-pending registers
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPENDSGIR2 CPENDSGIR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING3

SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


CPENDSGIR3

GICD SGI clear-pending registers
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPENDSGIR3 CPENDSGIR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING3

SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


SPENDSGIR0

GICD SGI set-pending registers
address_offset : 0xF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPENDSGIR0 SPENDSGIR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_SET_PENDING0 SGI_SET_PENDING1 SGI_SET_PENDING2 SGI_SET_PENDING3

SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


SPENDSGIR1

GICD SGI set-pending registers
address_offset : 0xF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPENDSGIR1 SPENDSGIR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_SET_PENDING0 SGI_SET_PENDING1 SGI_SET_PENDING2 SGI_SET_PENDING3

SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


SPENDSGIR2

GICD SGI set-pending registers
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPENDSGIR2 SPENDSGIR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_SET_PENDING0 SGI_SET_PENDING1 SGI_SET_PENDING2 SGI_SET_PENDING3

SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


SPENDSGIR3

GICD SGI set-pending registers
address_offset : 0xF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPENDSGIR3 SPENDSGIR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGI_SET_PENDING0 SGI_SET_PENDING1 SGI_SET_PENDING2 SGI_SET_PENDING3

SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)

SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)

SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)

SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)


PIDR4

GICD peripheral ID4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR4 PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR4

PIDR4 : peripheral ID4
bits : 0 - 31 (32 bit)


PIDR5

GICD peripheral ID5 register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR5 PIDR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR5

PIDR5 : peripheral ID5
bits : 0 - 31 (32 bit)


PIDR6

GICD peripheral ID6 register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR6 PIDR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR6

PIDR6 : peripheral ID6
bits : 0 - 31 (32 bit)


PIDR7

GICD peripheral ID7 register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR7 PIDR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR7

PIDR7 : peripheral ID7
bits : 0 - 31 (32 bit)


PIDR0

GICD peripheral ID0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR0 PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR0

PIDR0 : peripheral ID0
bits : 0 - 31 (32 bit)


PIDR1

GICD peripheral ID1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR1 PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR1

PIDR1 : peripheral ID1
bits : 0 - 31 (32 bit)


PIDR2

GICD peripheral ID2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR2 PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR2

PIDR2 : peripheral ID2
bits : 0 - 31 (32 bit)


PIDR3

GICD peripheral ID3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR3 PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR3

PIDR3 : peripheral ID3
bits : 0 - 31 (32 bit)


CIDR0

GICD component ID0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR0 CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIDR0

CIDR0 : component ID0
bits : 0 - 31 (32 bit)


CIDR1

GICD component ID1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR1 CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIDR1

CIDR1 : component ID1
bits : 0 - 31 (32 bit)


CIDR2

GICD component ID2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR2 CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIDR2

CIDR2 : component ID2
bits : 0 - 31 (32 bit)


CIDR3

GICD component ID3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR3 CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIDR3

CIDR3 : component ID3
bits : 0 - 31 (32 bit)



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