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AXIMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PERIPH_ID_4

PERIPH_ID_5

PERIPH_ID_6

PERIPH_ID_7

PERIPH_ID_0

PERIPH_ID_1

PERIPH_ID_2

PERIPH_ID_3

COMP_ID_0

COMP_ID_1

COMP_ID_2

COMP_ID_3

M0_FN_MOD2

M0_FN_MOD_AHB

M0_READ_QOS

M0_WRITE_QOS

M0_FN_MOD

M1_FN_MOD2

M1_FN_MOD_AHB

M1_READ_QOS

M1_WRITE_QOS

M1_FN_MOD

M2_FN_MOD2

M2_FN_MOD_AHB

M2_READ_QOS

M2_WRITE_QOS

M2_FN_MOD

M5_FN_MOD2

M5_FN_MOD_AHB

M5_READ_QOS

M5_WRITE_QOS

M5_FN_MOD

M3_READ_QOS

M3_WRITE_QOS

M3_FN_MOD

M7_READ_QOS

M7_WRITE_QOS

M7_FN_MOD

M8_READ_QOS

M8_WRITE_QOS

M8_FN_MOD

FN_MOD_LB

M4_READ_QOS

M4_WRITE_QOS

M4_FN_MOD

M9_READ_QOS

M9_WRITE_QOS

M9_FN_MOD

M10_READ_QOS

M10_WRITE_QOS

M10_FN_MOD

M6_FN_MOD_AHB

M6_READ_QOS

M6_WRITE_QOS

M6_FN_MOD


PERIPH_ID_4

AXIMC peripheral ID4 register
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_4 PERIPH_ID_4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106CON KCOUNT4

JEP106CON : JEP106 continuation code
bits : 0 - 3 (4 bit)

KCOUNT4 : register file size
bits : 4 - 7 (4 bit)


PERIPH_ID_5

AXIMC peripheral ID5 register
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_5 PERIPH_ID_5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ID_5

PERIPH_ID_5 : not used
bits : 0 - 7 (8 bit)


PERIPH_ID_6

AXIMC peripheral ID6 register
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_6 PERIPH_ID_6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ID_6

PERIPH_ID_6 : not used
bits : 0 - 7 (8 bit)


PERIPH_ID_7

AXIMC peripheral ID7 register
address_offset : 0x1FDC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_7 PERIPH_ID_7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ID_7

PERIPH_ID_7 : not used
bits : 0 - 7 (8 bit)


PERIPH_ID_0

AXIMC peripheral ID0 register
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_0 PERIPH_ID_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ID_0

PERIPH_ID_0 : part number
bits : 0 - 7 (8 bit)


PERIPH_ID_1

AXIMC peripheral ID1 register
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_1 PERIPH_ID_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ID_1

PERIPH_ID_1 : part number
bits : 0 - 7 (8 bit)


PERIPH_ID_2

AXIMC peripheral ID2 register
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_2 PERIPH_ID_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ID_2

PERIPH_ID_2 : part number
bits : 0 - 7 (8 bit)


PERIPH_ID_3

AXIMC peripheral ID3 register
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ID_3 PERIPH_ID_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUST_MOD_NUM REV_AND

CUST_MOD_NUM : customer modification
bits : 0 - 3 (4 bit)

REV_AND : customer version
bits : 4 - 7 (4 bit)


COMP_ID_0

AXIMC component ID0 register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMP_ID_0 COMP_ID_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : preamble bits
bits : 0 - 7 (8 bit)


COMP_ID_1

AXIMC component ID1 register
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMP_ID_1 COMP_ID_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE CLASS

PREAMBLE : preamble bits
bits : 0 - 3 (4 bit)

CLASS : Component class
bits : 4 - 7 (4 bit)


COMP_ID_2

AXIMC component ID2 register
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMP_ID_2 COMP_ID_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : preamble bits
bits : 0 - 7 (8 bit)


COMP_ID_3

AXIMC component ID3 register
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMP_ID_3 COMP_ID_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : preamble bits
bits : 0 - 7 (8 bit)


M0_FN_MOD2

AXIMC master 0 packing functionality register
address_offset : 0x42024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M0_FN_MOD2 M0_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)


M0_FN_MOD_AHB

AXIMC master 0 AHB conversion override functionality register
address_offset : 0x42028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M0_FN_MOD_AHB M0_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : Converts all AHB-Lite write transactions
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : Converts all AHB-Lite read transactions
bits : 1 - 1 (1 bit)


M0_READ_QOS

AXIMC master 0 read priority register
address_offset : 0x42100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M0_READ_QOS M0_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M0_WRITE_QOS

AXIMC master 0 write priority register
address_offset : 0x42104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M0_WRITE_QOS M0_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M0_FN_MOD

AXIMC master 0 issuing capability override functionality register
address_offset : 0x42108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M0_FN_MOD M0_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M1_FN_MOD2

AXIMC master 1 packing functionality register
address_offset : 0x43024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1_FN_MOD2 M1_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)


M1_FN_MOD_AHB

AXIMC master 1 AHB conversion override functionality register
address_offset : 0x43028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1_FN_MOD_AHB M1_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : Converts all AHB-Lite write transactions
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : Converts all AHB-Lite read transactions
bits : 1 - 1 (1 bit)


M1_READ_QOS

AXIMC master 1 read priority register
address_offset : 0x43100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1_READ_QOS M1_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M1_WRITE_QOS

AXIMC master 1 write priority register
address_offset : 0x43104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1_WRITE_QOS M1_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M1_FN_MOD

AXIMC master 1 issuing capability override functionality register
address_offset : 0x43108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1_FN_MOD M1_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M2_FN_MOD2

AXIMC master 2 packing functionality register
address_offset : 0x44024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2_FN_MOD2 M2_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)


M2_FN_MOD_AHB

AXIMC master 2 AHB conversion override functionality register
address_offset : 0x44028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2_FN_MOD_AHB M2_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : Converts all AHB-Lite write transactions
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : Converts all AHB-Lite read transactions
bits : 1 - 1 (1 bit)


M2_READ_QOS

AXIMC master 2 read priority register
address_offset : 0x44100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2_READ_QOS M2_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M2_WRITE_QOS

AXIMC master 2 write priority register
address_offset : 0x44104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2_WRITE_QOS M2_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M2_FN_MOD

AXIMC master 2 issuing capability override functionality register
address_offset : 0x44108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2_FN_MOD M2_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M5_FN_MOD2

AXIMC master 5 packing functionality register
address_offset : 0x45024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5_FN_MOD2 M5_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)


M5_FN_MOD_AHB

AXIMC master 5 AHB conversion override functionality register
address_offset : 0x45028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5_FN_MOD_AHB M5_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : converts all AHB-Lite write transactions to a series of single beat
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : converts all AHB-Lite read transactions to a series of single beat
bits : 1 - 1 (1 bit)


M5_READ_QOS

AXIMC master 5 read priority register
address_offset : 0x45100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5_READ_QOS M5_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M5_WRITE_QOS

AXIMC master 5 write priority register
address_offset : 0x45104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5_WRITE_QOS M5_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M5_FN_MOD

AXIMC master 5 issuing capability override functionality register
address_offset : 0x45108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5_FN_MOD M5_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M3_READ_QOS

AXIMC master 3 read priority register
address_offset : 0x46100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3_READ_QOS M3_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M3_WRITE_QOS

AXIMC master 3 write priority register
address_offset : 0x46104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3_WRITE_QOS M3_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M3_FN_MOD

AXIMC master 3 packing functionality register
address_offset : 0x46108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3_FN_MOD M3_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M7_READ_QOS

AXIMC master 7 read priority register
address_offset : 0x47100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M7_READ_QOS M7_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M7_WRITE_QOS

AXIMC master 7 write priority register
address_offset : 0x47104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M7_WRITE_QOS M7_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M7_FN_MOD

AXIMC master 7 issuing capability override functionality register
address_offset : 0x47108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M7_FN_MOD M7_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M8_READ_QOS

AXIMC master 8 read priority register
address_offset : 0x48100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M8_READ_QOS M8_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M8_WRITE_QOS

AXIMC master 8 write priority register
address_offset : 0x48104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M8_WRITE_QOS M8_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M8_FN_MOD

AXIMC master 8 issuing capability override functionality register
address_offset : 0x48108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M8_FN_MOD M8_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


FN_MOD_LB

AXIMC long burst capability inhibition register
address_offset : 0x4A02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FN_MOD_LB FN_MOD_LB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FN_MOD_LB

FN_MOD_LB : controls burst breaking of long bursts
bits : 0 - 0 (1 bit)


M4_READ_QOS

AXIMC master 4 read priority register
address_offset : 0x4A100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M4_READ_QOS M4_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M4_WRITE_QOS

AXIMC master 4 write priority register
address_offset : 0x4A104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M4_WRITE_QOS M4_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M4_FN_MOD

AXIMC master 4 packing functionality register
address_offset : 0x4A108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M4_FN_MOD M4_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M9_READ_QOS

AXIMC master 9 read priority register
address_offset : 0x4B100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M9_READ_QOS M9_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M9_WRITE_QOS

AXIMC master 9 write priority register
address_offset : 0x4B104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M9_WRITE_QOS M9_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M9_FN_MOD

AXIMC master 9 issuing capability override functionality register
address_offset : 0x4B108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M9_FN_MOD M9_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M10_READ_QOS

AXIMC master 10 read priority register
address_offset : 0x4C100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M10_READ_QOS M10_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M10_WRITE_QOS

AXIMC master 10 write priority register
address_offset : 0x4C104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M10_WRITE_QOS M10_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M10_FN_MOD

AXIMC master 10 issuing capability override functionality register
address_offset : 0x4C108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M10_FN_MOD M10_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)


M6_FN_MOD_AHB

AXIMC master 6 AHB conversion override functionality register
address_offset : 0x4D028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M6_FN_MOD_AHB M6_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : converts all AHB-Lite write transactions to a series of single beat
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : converts all AHB-Lite read transactions to a series of single beat
bits : 1 - 1 (1 bit)


M6_READ_QOS

AXIMC master 6 read priority register
address_offset : 0x4D100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M6_READ_QOS M6_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)


M6_WRITE_QOS

AXIMC master 6 write priority register
address_offset : 0x4D104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M6_WRITE_QOS M6_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)


M6_FN_MOD

AXIMC master 6 issuing capability override functionality register
address_offset : 0x4D108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M6_FN_MOD M6_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)



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