\n
address_offset : 0x0 Bytes (0x0)
size : 0x100000 byte (0x0)
mem_usage : registers
protection : not protected
AXIMC peripheral ID4 register
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEP106CON : JEP106 continuation code
bits : 0 - 3 (4 bit)
KCOUNT4 : register file size
bits : 4 - 7 (4 bit)
AXIMC peripheral ID5 register
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_5 : not used
bits : 0 - 7 (8 bit)
AXIMC peripheral ID6 register
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_6 : not used
bits : 0 - 7 (8 bit)
AXIMC peripheral ID7 register
address_offset : 0x1FDC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_7 : not used
bits : 0 - 7 (8 bit)
AXIMC peripheral ID0 register
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_0 : part number
bits : 0 - 7 (8 bit)
AXIMC peripheral ID1 register
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_1 : part number
bits : 0 - 7 (8 bit)
AXIMC peripheral ID2 register
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_2 : part number
bits : 0 - 7 (8 bit)
AXIMC peripheral ID3 register
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUST_MOD_NUM : customer modification
bits : 0 - 3 (4 bit)
REV_AND : customer version
bits : 4 - 7 (4 bit)
AXIMC component ID0 register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : preamble bits
bits : 0 - 7 (8 bit)
AXIMC component ID1 register
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : preamble bits
bits : 0 - 3 (4 bit)
CLASS : Component class
bits : 4 - 7 (4 bit)
AXIMC component ID2 register
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : preamble bits
bits : 0 - 7 (8 bit)
AXIMC component ID3 register
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : preamble bits
bits : 0 - 7 (8 bit)
AXIMC master 0 packing functionality register
address_offset : 0x42024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)
AXIMC master 0 AHB conversion override functionality register
address_offset : 0x42028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : Converts all AHB-Lite write transactions
bits : 0 - 0 (1 bit)
WR_INC_OVERRIDE : Converts all AHB-Lite read transactions
bits : 1 - 1 (1 bit)
AXIMC master 0 read priority register
address_offset : 0x42100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 0 write priority register
address_offset : 0x42104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 0 issuing capability override functionality register
address_offset : 0x42108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 1 packing functionality register
address_offset : 0x43024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)
AXIMC master 1 AHB conversion override functionality register
address_offset : 0x43028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : Converts all AHB-Lite write transactions
bits : 0 - 0 (1 bit)
WR_INC_OVERRIDE : Converts all AHB-Lite read transactions
bits : 1 - 1 (1 bit)
AXIMC master 1 read priority register
address_offset : 0x43100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 1 write priority register
address_offset : 0x43104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 1 issuing capability override functionality register
address_offset : 0x43108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 2 packing functionality register
address_offset : 0x44024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)
AXIMC master 2 AHB conversion override functionality register
address_offset : 0x44028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : Converts all AHB-Lite write transactions
bits : 0 - 0 (1 bit)
WR_INC_OVERRIDE : Converts all AHB-Lite read transactions
bits : 1 - 1 (1 bit)
AXIMC master 2 read priority register
address_offset : 0x44100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 2 write priority register
address_offset : 0x44104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 2 issuing capability override functionality register
address_offset : 0x44108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 5 packing functionality register
address_offset : 0x45024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : Disable packing of beats to match the output data
bits : 0 - 0 (1 bit)
AXIMC master 5 AHB conversion override functionality register
address_offset : 0x45028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : converts all AHB-Lite write transactions to a series of single beat
bits : 0 - 0 (1 bit)
WR_INC_OVERRIDE : converts all AHB-Lite read transactions to a series of single beat
bits : 1 - 1 (1 bit)
AXIMC master 5 read priority register
address_offset : 0x45100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 5 write priority register
address_offset : 0x45104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 5 issuing capability override functionality register
address_offset : 0x45108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 3 read priority register
address_offset : 0x46100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 3 write priority register
address_offset : 0x46104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 3 packing functionality register
address_offset : 0x46108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 7 read priority register
address_offset : 0x47100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 7 write priority register
address_offset : 0x47104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 7 issuing capability override functionality register
address_offset : 0x47108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 8 read priority register
address_offset : 0x48100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 8 write priority register
address_offset : 0x48104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 8 issuing capability override functionality register
address_offset : 0x48108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC long burst capability inhibition register
address_offset : 0x4A02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FN_MOD_LB : controls burst breaking of long bursts
bits : 0 - 0 (1 bit)
AXIMC master 4 read priority register
address_offset : 0x4A100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 4 write priority register
address_offset : 0x4A104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 4 packing functionality register
address_offset : 0x4A108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 9 read priority register
address_offset : 0x4B100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 9 write priority register
address_offset : 0x4B104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 9 issuing capability override functionality register
address_offset : 0x4B108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 10 read priority register
address_offset : 0x4C100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 10 write priority register
address_offset : 0x4C104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 10 issuing capability override functionality register
address_offset : 0x4C108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
AXIMC master 6 AHB conversion override functionality register
address_offset : 0x4D028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : converts all AHB-Lite write transactions to a series of single beat
bits : 0 - 0 (1 bit)
WR_INC_OVERRIDE : converts all AHB-Lite read transactions to a series of single beat
bits : 1 - 1 (1 bit)
AXIMC master 6 read priority register
address_offset : 0x4D100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : read channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 6 write priority register
address_offset : 0x4D104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : write channel QoS setting
bits : 0 - 3 (4 bit)
AXIMC master 6 issuing capability override functionality register
address_offset : 0x4D108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : override AMIB read issuing capability
bits : 0 - 0 (1 bit)
WRITE_ISS_OVERRIDE : override AMIB write issuing capability
bits : 1 - 1 (1 bit)
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