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TZC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BUILD_CONFIG

INT_STATUS

REGION_BASE_LOW0

REGION_TOP_LOW0

REGION_ATTRIBUTE0

REGION_ID_ACCESS0

REGION_BASE_LOW1

REGION_TOP_LOW1

REGION_ATTRIBUTE1

REGION_ID_ACCESS1

INT_CLEAR

REGION_BASE_LOW2

REGION_TOP_LOW2

REGION_ATTRIBUTE2

REGION_ID_ACCESS2

REGION_BASE_LOW3

REGION_TOP_LOW3

REGION_ATTRIBUTE3

REGION_ID_ACCESS3

REGION_BASE_LOW4

REGION_TOP_LOW4

REGION_ATTRIBUTE4

REGION_ID_ACCESS4

REGION_BASE_LOW5

REGION_TOP_LOW5

REGION_ATTRIBUTE5

REGION_ID_ACCESS5

REGION_BASE_LOW6

REGION_TOP_LOW6

REGION_ATTRIBUTE6

REGION_ID_ACCESS6

REGION_BASE_LOW7

REGION_TOP_LOW7

REGION_ATTRIBUTE7

REGION_ID_ACCESS7

FAIL_ADDRESS_LOW0

REGION_BASE_LOW8

REGION_TOP_LOW8

REGION_ATTRIBUTE8

REGION_ID_ACCESS8

FAIL_CONTROL0

FAIL_ID0

FAIL_ADDRESS_LOW1

FAIL_CONTROL1

FAIL_ID1

ACTION

GATE_KEEPER

SPECULATION_CTRL

PID4

PID5

PID6

PID7

PID0

PID1

PID2

PID3

CID0

CID1

CID2

CID3


BUILD_CONFIG

TZC configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUILD_CONFIG BUILD_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NO_OF_REGIONS ADDRESS_WIDTH NO_OF_FILTERS

NO_OF_REGIONS : Number fo regions
bits : 0 - 4 (5 bit)

ADDRESS_WIDTH : ADDRESS WIDTH
bits : 8 - 13 (6 bit)

NO_OF_FILTERS : Number of filters
bits : 24 - 25 (2 bit)


INT_STATUS

TZC interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS OVERRUN OVERLAP

STATUS : Interrupt status for each filter
bits : 0 - 0 (1 bit)

OVERRUN : Permission failure overrun
bits : 8 - 9 (2 bit)

OVERLAP : Overlap violation for each filter
bits : 16 - 17 (2 bit)


REGION_BASE_LOW0

TZC region 0 base address low register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW0 REGION_BASE_LOW0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : base address bits
bits : 12 - 31 (20 bit)


REGION_TOP_LOW0

TZC region 0 top address low register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW0 REGION_TOP_LOW0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Top address bits
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE0

TZC region 0 attribute register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE0 REGION_ATTRIBUTE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS0

TZC region 0 ID access register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS0 REGION_ID_ACCESS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


REGION_BASE_LOW1

TZC region 1 ID access register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW1 REGION_BASE_LOW1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW1

TZC regions 1 top address low register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW1 REGION_TOP_LOW1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE1

TZC region 2 attribute register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE1 REGION_ATTRIBUTE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS1

TZC region 1 ID access register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS1 REGION_ID_ACCESS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


INT_CLEAR

TZC interrupt clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INT_CLEAR INT_CLEAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLEAR

CLEAR : Filter interrupt clear
bits : 0 - 1 (2 bit)


REGION_BASE_LOW2

TZC region 2 ID access register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW2 REGION_BASE_LOW2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW2

TZC regions 2 top address low register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW2 REGION_TOP_LOW2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE2

TZC region 2 attribute register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE2 REGION_ATTRIBUTE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS2

TZC region 2 ID access register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS2 REGION_ID_ACCESS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


REGION_BASE_LOW3

TZC region 3 ID access register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW3 REGION_BASE_LOW3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW3

TZC regions 3 top address low register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW3 REGION_TOP_LOW3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE3

TZC region 3 attribute register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE3 REGION_ATTRIBUTE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS3

TZC region 3 ID access register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS3 REGION_ID_ACCESS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


REGION_BASE_LOW4

TZC region 4 ID access register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW4 REGION_BASE_LOW4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW4

TZC regions 4 top address low register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW4 REGION_TOP_LOW4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE4

TZC region 4 attribute register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE4 REGION_ATTRIBUTE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS4

TZC region 4 ID access register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS4 REGION_ID_ACCESS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


REGION_BASE_LOW5

TZC region 5 ID access register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW5 REGION_BASE_LOW5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW5

TZC regions 5 top address low register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW5 REGION_TOP_LOW5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE5

TZC region 5 attribute register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE5 REGION_ATTRIBUTE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS5

TZC region 5 ID access register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS5 REGION_ID_ACCESS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


REGION_BASE_LOW6

TZC region 6 ID access register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW6 REGION_BASE_LOW6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW6

TZC regions 6 top address low register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW6 REGION_TOP_LOW6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE6

TZC region 6 attribute register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE6 REGION_ATTRIBUTE6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS6

TZC region 6 ID access register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS6 REGION_ID_ACCESS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


REGION_BASE_LOW7

TZC region 7 ID access register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW7 REGION_BASE_LOW7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW7

TZC regions 7 top address low register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW7 REGION_TOP_LOW7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE7

TZC region 7 attribute register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE7 REGION_ATTRIBUTE7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS7

TZC region 7 ID access register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS7 REGION_ID_ACCESS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


FAIL_ADDRESS_LOW0

TZC fail address low register0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAIL_ADDRESS_LOW0 FAIL_ADDRESS_LOW0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_STATUS_LOW

ADDR_STATUS_LOW : Fail address low bits
bits : 0 - 31 (32 bit)


REGION_BASE_LOW8

TZC region 8 ID access register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_BASE_LOW8 REGION_BASE_LOW8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDRESS_LOW

BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_TOP_LOW8

TZC regions 8 top address low register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_TOP_LOW8 REGION_TOP_LOW8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP_ADDRESS_LOW

TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)


REGION_ATTRIBUTE8

TZC region 8 attribute register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ATTRIBUTE8 REGION_ATTRIBUTE8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER_EN S_RD_EN S_WR_EN

FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)

S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)

S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)


REGION_ID_ACCESS8

TZC region 8 ID access register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGION_ID_ACCESS8 REGION_ID_ACCESS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAID_RD_EN NSAID_WR_EN

NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)

NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)


FAIL_CONTROL0

TZC fail control register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAIL_CONTROL0 FAIL_CONTROL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIVILEGE NON_SECURE DIRECTION

PRIVILEGE : Privilege access failure
bits : 20 - 20 (1 bit)

NON_SECURE : Non-secure access failure
bits : 21 - 21 (1 bit)

DIRECTION : Access failure direction
bits : 24 - 24 (1 bit)


FAIL_ID0

TZC fail ID register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAIL_ID0 FAIL_ID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : AXI fail ID
bits : 0 - 10 (11 bit)


FAIL_ADDRESS_LOW1

TZC fail address low register1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAIL_ADDRESS_LOW1 FAIL_ADDRESS_LOW1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_STATUS_LOW

ADDR_STATUS_LOW : Fail address low bits
bits : 0 - 31 (32 bit)


FAIL_CONTROL1

TZC fail control register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAIL_CONTROL1 FAIL_CONTROL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIVILEGE NON_SECURE DIRECTION

PRIVILEGE : Privilege access failure
bits : 20 - 20 (1 bit)

NON_SECURE : Non-secure access failure
bits : 21 - 21 (1 bit)

DIRECTION : Access failure direction
bits : 24 - 24 (1 bit)


FAIL_ID1

TZC fail ID register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAIL_ID1 FAIL_ID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : AXI fail ID
bits : 0 - 10 (11 bit)


ACTION

TZC action register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTION ACTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REACTION_VALUE

REACTION_VALUE : Permission failure reaction
bits : 0 - 1 (2 bit)


GATE_KEEPER

TZC gate keeper register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GATE_KEEPER GATE_KEEPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPENREQ OPENSTAT

OPENREQ : Gate keeper open request
bits : 0 - 1 (2 bit)

OPENSTAT : Gate keeper status for each filter
bits : 16 - 17 (2 bit)


SPECULATION_CTRL

TZC speculation control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPECULATION_CTRL SPECULATION_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READSPEC_DISABLE WRITESPEC_DISABLE

READSPEC_DISABLE : Read access speculation disable
bits : 0 - 0 (1 bit)

WRITESPEC_DISABLE : Write access speculation disable
bits : 1 - 1 (1 bit)


PID4

TZC peripheral ID 4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID4 PID4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_4

PER_ID_4 : Peripheral ID 4
bits : 0 - 7 (8 bit)


PID5

TZC peripheral ID 5 register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID5 PID5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_5

PER_ID_5 : Peripheral ID 5
bits : 0 - 7 (8 bit)


PID6

TZC peripheral ID 6 register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID6 PID6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_6

PER_ID_6 : Peripheral ID 6
bits : 0 - 7 (8 bit)


PID7

TZC peripheral ID 7 register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID7 PID7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_7

PER_ID_7 : Peripheral ID 7
bits : 0 - 7 (8 bit)


PID0

TZC peripheral ID 0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID0 PID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_0

PER_ID_0 : Peripheral ID 0
bits : 0 - 7 (8 bit)


PID1

TZC peripheral ID 1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID1 PID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_1

PER_ID_1 : Peripheral ID 1
bits : 0 - 7 (8 bit)


PID2

TZC peripheral ID 2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID2 PID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_2

PER_ID_2 : Peripheral ID 2
bits : 0 - 7 (8 bit)


PID3

TZC peripheral ID 3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID3 PID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER_ID_3

PER_ID_3 : Peripheral ID 3
bits : 0 - 7 (8 bit)


CID0

TZC component ID 0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID0 CID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_ID_0

COMP_ID_0 : Component ID 0
bits : 0 - 7 (8 bit)


CID1

TZC component ID 1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID1 CID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_ID_1

COMP_ID_1 : Component ID 1
bits : 0 - 7 (8 bit)


CID2

TZC component ID 2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID2 CID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_ID_2

COMP_ID_2 : Component ID 2
bits : 0 - 7 (8 bit)


CID3

TZC component ID 3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID3 CID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_ID_3

COMP_ID_3 : Component ID 3
bits : 0 - 7 (8 bit)



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